ispLSI 3256A Device Datasheet June 2010 All Devices Discontinued Product Change Notification (PCN) 09-10 has been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN ispLSI 3256A-70LQ ispLSI 3256A ispLSI 3256A-90LQ Discontinued PCN 09-10 ispLSI 3256A-70LQI 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: ispLSI 3256A In-System Programmable High Density PLD Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC 128 I/O Pins Output Routing Pool Output Routing Pool Boundary Scan 11000 PLD Gates H3 H2 H1 H0 G3 G2 G1 G0 384 Registers A0 F3 DQ High Speed Global Interconnect Wide Input Gating for Fast Counters, State DQ A1 F2 OR Machines, Address Decoders, etc. Array DQ A2 F1 Small Logic Block Size for Random Logic DQ 2 Twin HIGH-PERFORMANCE E CMOS TECHNOLOGY A3 F0 GLB DQ fmax = 90 MHz Maximum Operating Frequency tpd = 12 ns Propagation Delay DQ OR TTL Compatible Inputs and Outputs B0 E3 Array DQ Electrically Erasable and Reprogrammable B1 E2 DQ Non-Volatile 100% Tested at Time of Manufacture B2 E1 Unused Product Term Shutdown Saves Power Global Routing Pool B3 E0 IN-SYSTEM PROGRAMMABLE 5V In-System Programmable (ISP) using Lattice C0 C1 C2 C3 D0 D1 D2 D3 ISP or Boundary Scan Test (IEEE 1149.1) Protocol Output Routing Pool Output Routing Pool Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality 0139A Reprogram Soldered Devices for Faster Debugging Description 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE The ispLSI 3256A is a High-Density Programmable Logic OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY Device containing 384 Registers, 128 Universal I/O pins, OF FIELD PROGRAMMABLE GATE ARRAYS five Dedicated Clock Input Pins, eight Output Routing Complete Programmable Device Can Combine Glue Pools (ORP) and a Global Routing Pool (GRP) which Logic and Structured Designs allows complete inter-connectivity between all of these Enhanced Pin Locking Capability elements. The ispLSI 3256A features 5V in-system Five Dedicated Clock Input Pins programmability and in-system diagnostic capabilities. Synchronous and Asynchronous Clocks The ispLSI 3256A offers non-volatile reprogrammability Programmable Output Slew Rate Control to Mini- of the logic, as well as the interconnect to provide truly mize Switching Noise reconfigurable systems. Flexible Pin Placement Optimized Global Routing Pool Provides Global The basic unit of logic on the ispLSI 3256A device is the Interconnectivity Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3. ispDesignEXPERT LOGIC COMPILER AND COM- There are a total of 32 Twin GLBs in the ispLSI 3256A PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL device. Each Twin GLB has 24 inputs, a programmable SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING AND array and two OR/Exclusive-OR Arrays, and eight Superior Quality of Results outputs which can be configured to be either combinato- Tightly Integrated with Leading CAE Vendor Tools rial or registered. All Twin GLB inputs come from the Productivity Enhancing Timing Analyzer, Explore GRP. Tools, Timing Simulator and ispANALYZER PC and UNIX Platforms Copyright 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. May 1999 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556