ispLSI 3256E Device Datasheet June 2010 All Devices Discontinued Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN ispLSI 3256E-70LB320 PCN 09-10 ispLSI 3256E-100LB320 ispLSI 3256E Discontinued ispLSI 3256E-70LQA PCN 12-09 ispLSI 3256E-100LQA 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: ispLSI 3256E In-System Programmable High Density PLD Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC 256 I/O Pins ORP ORP ORP ORP Boundary 12000 PLD Gates Scan H3 H2 H1 H0 G3 G2 G1 G0 512 Registers High Speed Global Interconnect A0 F3 DQ Wide Input Gating for Fast Counters, State A1 DQ F2 Machines, Address Decoders, etc. OR Small Logic Block Size for Random Logic Array DQ A2 F1 2 HIGH PERFORMANCE E CMOS TECHNOLOGY DQ Twin A3 F0 fmax = 100 MHz Maximum Operating Frequency GLB DQ tpd = 10 ns Propagation Delay DQ TTL Compatible Inputs and Outputs OR Electrically Erasable and Reprogrammable B0 E3 Array DQ Non-Volatile B1 E2 DQ 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power B2 E1 Global Routing Pool IN-SYSTEM PROGRAMMABLE B3 E0 5V In-System Programmable (ISP) using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol C0 C1 C2 C3 D0 D1 D2 D3 Increased Manufacturing Yields, Reduced Time-to- ORP ORP ORP ORP Market, and Improved Product Quality Reprogram Soldered Devices for Faster Debugging 0139A/3256E 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE Description OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY The ispLSI 3256E is a High Density Programmable Logic OF FIELD PROGRAMMABLE GATE ARRAYS Device containing 512 Registers, 256 Universal I/O pins, Complete Programmable Device Can Combine Glue five Dedicated Clock Input Pins, 16 Output Routing Pools Logic and Structured Designs (ORP) and a Global Routing Pool (GRP) which allows Five Dedicated Clock Input Pins complete inter-connectivity between all of these ele- Synchronous and Asynchronous Clocks ments. The ispLSI 3256E features 5V in-system Programmable Output Slew Rate Control to Mini- mize Switching Noise programmability and in-system diagnostic capabilities. Flexible Pin Placement The ispLSI 3256E offers non-volatile reprogrammability Optimized Global Routing Pool Provides Global of the logic, as well as the interconnect to provide truly Interconnectivity reconfigurable systems. ispDesignEXPERT LOGIC COMPILER AND COM- The basic unit of logic on the ispLSI 3256E device is the PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3. SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING There are a total of 32 Twin GLBs in the ispLSI 3256E Superior Quality of Results device. Each Twin GLB has 24 inputs, a programmable Tightly Integrated with Leading CAE Vendor Tools AND array and two OR/Exclusive-OR Arrays and eight Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER outputs which can be configured to be either combinato- PC and UNIX Platforms rial or registered. All Twin GLB inputs come from the GRP. Copyright 2010 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. March 2010 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556