ispLSI 3320 Device Datasheet June 2010 All Devices Discontinued Product Change Notification (PCN) 09-10 has been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN ispLSI 3320-70LQ ispLSI 3320-100LQ ispLSI 3320 Discontinued PCN 09-10 ispLSI 3320-70LB320 ispLSI 3320-100LB320 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: ispLSI 3320 In-System Programmable High Density PLD Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC Output Routing Pool (ORP) Output Routing Pool (ORP) 160 I/O Pins Boundary Scan G3 G2 G1 G0 F3 F2 F1 F0 14000 PLD Gates 480 Registers H0 E3 DQ High Speed Global Interconnect DQ H1 E2 Wide Input Gating for Fast Counters, State OR Array DQ Machines, Address Decoders, etc. H2 E1 Small Logic Block Size for Random Logic DQ 2 H3 Twin E0 HIGH-PERFORMANCE E CMOS TECHNOLOGY DQ GLB fmax = 100 MHz Maximum Operating Frequency DQ OR I0 D3 tpd = 10 ns Propagation Delay Array DQ TTL Compatible Inputs and Outputs D2 I1 DQ Electrically Erasable and Reprogrammable D1 Non-Volatile I2 100% Tested at Time of Manufacture I3 D0 Unused Product Term Shutdown Saves Power ispLSI FEATURES: J0 C3 5V In-System Programmable (ISP) Using Lattice Global Routing Pool J1 C2 ISP or Boundary Scan Test (IEEE 1149.1) Protocol (GRP) Increased Manufacturing Yields, Reduced Time-to- J2 C1 Market, and Improved Product Quality Reprogram Soldered Devices for Faster Debugging J3 C0 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE A0 A1 A2 A3 B0 B1 B2 B3 Output Routing Pool (ORP) Output Routing Pool (ORP) OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY 0139/3320 OF FIELD PROGRAMMABLE GATE ARRAYS Description Complete Programmable Device Can Combine Glue Logic and Structured Designs The ispLSI 3320 is a High-Density Programmable Logic Enhanced Pin Locking Capability Device containing 480 Registers, 160 Universal I/O pins, Five Dedicated Clock Input Pins Synchronous and Asynchronous Clocks five Dedicated Clock Input Pins, ten Output Routing Programmable Output Slew Rate Control to Pools (ORP) and a Global Routing Pool (GRP) which Minimize Switching Noise allows complete inter-connectivity between all of these Flexible Pin Placement elements. The ispLSI 3320 features 5V in-system pro- Optimized Global Routing Pool Provides Global grammability and in-system diagnostic capabilities. The Interconnectivity ispLSI 3320 offers non-volatile reprogrammability of the Pin Compatible with ispLSI 3160 logic, as well as the interconnect to provide truly ispDesignEXPERT LOGIC COMPILER AND COM- reconfigurable systems. PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL The basic unit of logic on the ispLSI 3320 device is the SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Twin Generic Logic Block (Twin GLB) labelled A0, A1...J3. Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools There are a total of 40 of these Twin GLBs in the ispLSI Productivity Enhancing Timing Analyzer, Explore 3320 device. Each Twin GLB has 24 inputs, a program- Tools, Timing Simulator and ispANALYZER mable AND array and two OR/Exclusive-OR Arrays, and PC and UNIX Platforms eight outputs which can be configured to be either com- binatorial or registered. All Twin GLB inputs come from the GRP. Copyright 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 2003 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556