Input Bus Generic Logic Block ispLSI 5128VE In-System Programmable 3.3V SuperWIDE High Density PLD Features Functional Block Diagram Second Generation SuperWIDE HIGH DENSITY Input Bus IN-SYSTEM PROGRAMMABLE LOGIC DEVICE Boundary 3.3V Power Supply Scan Generic Interface Logic Block User Selectable 3.3V/2.5V I/O 6000 PLD Gates / 128 Macrocells 96 I/O Pins Available 128 Registers High-Speed Global Interconnect SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance SuperWIDE Input Gating (68 Inputs) for Fast Global Routing Pool Counters, State Machines, Address Decoders, etc. (GRP) Interfaces with Standard 5V TTL Devices 2 HIGH PERFORMANCE E CMOS TECHNOLOGY fmax = 180 MHz Maximum Operating Frequency tpd = 5.0 ns Propagation Delay TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels Electrically Erasable and Reprogrammable Non-Volatile Generic Logic Block Programmable Speed/Power Logic Path Optimization Input Bus IN-SYSTEM PROGRAMMABLE Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality Reprogram Soldered Devices for Faster Debugging ispLSI 5000VE Description 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND The ispLSI 5000VE Family of In-System Programmable 3.3V IN-SYSTEM PROGRAMMABLE High Density Logic Devices is based on Generic Logic ARCHITECTURE FEATURES Blocks (GLBs) of 32 registered macrocells and a single Enhanced Pin-Locking Architecture with Single- Global Routing Pool (GRP) structure interconnecting the Level Global Routing Pool and SuperWIDE GLBs GLBs. Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell Outputs from the GLBs drive the Global Routing Pool Macrocells Support Concurrent Combinatorial and Registered Functions (GRP) between the GLBs. Switching resources are pro- Macrocell Registers Feature Multiple Control vided to allow signals in the Global Routing Pool to drive Options Including Set, Reset and Clock Enable any or all the GLBs in the device. This mechanism allows Four Dedicated Clock Input Pins Plus Macrocell fast, efficient connections across the entire device. Product Term Clocks Programmable I/O Supports Programmable Bus Each GLB contains 32 macrocells and a fully populated, Hold, Pull-up, Open Drain and Slew Rate Options programmable AND-array with 160 logic product terms Four Global Product Term Output Enables, Two and three extra control product terms. The GLB has 68 Global OE Pins and One Product Term OE per inputs from the Global Routing Pool which are available Macrocell in both true and complement form for every product term. The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be by- passed for functions of five product terms or less. The three extra product terms are used for shared controls: reset, clock, clock enable and output enable. Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Input Bus Generic Logic Block Specifications ispLSI 5128VE Functional Block Diagram Figure 1. ispLSI 5128VE Functional Block Diagram (96-I/O) Input Bus TDI Boundary TDO Scan Generic Interface VCCIO Logic Block I/O 71 1 TOE I/O 70 I/O 1 I/O 69 I/O 2 I/O 68 I/O 3 Global Routing Pool (GRP) I/O 51 I/O 20 I/O 50 I/O 21 I/O 49 I/O 22 I/O 48 I/O 23 Generic Logic Block Input Bus RESET 1. CLK2, CLK3 and TOE signals are shared with I/O signals. Use the table below to determine which I/O is shared. Package Type Multplexed Signals 128 TQFP I/O 59 / CLK2 I/O 65 / CLK3 I/O 0 / TOE 2 GOE0 Input Bus GOE1 Generic Logic Block I/O 95 I/O 24 I/O 94 I/O 25 I/O 93 I/O 26 I/O 92 I/O 27 I/O 75 I/O 44 I/O 74 I/O 45 I/O 73 I/O 46 I/O 72 I/O 47 CLK0 CLK1 TCK 1 CLK2 TMS 1 CLK3