Input Bus Input Bus
Generic Generic
Logic Block
Logic Block
ispLSI 5256VA
In-System Programmable
3.3V SuperWIDE High Density PLD
Features Functional Block Diagram
SuperWIDE HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
Input Bus Input Bus
Boundary
3.3V Power Supply
Scan
Generic Generic
User Selectable 3.3V/2.5V I/O
Interface
Logic Block Logic Block
12000 PLD Gates / 256 Macrocells
Up to 192 I/O Pins
256 Registers
High-Speed Global Interconnect
SuperWIDE 32 Generic Logic Block (GLB) Size for
Optimum Performance
SuperWIDE Input Gating (68 Inputs) for Fast
Counters, State Machines, Address Decoders, etc.
Global Routing Pool
PCB Efficient Ball Grid Array (BGA) Package Options (GRP)
Interfaces with Standard 5V TTL Devices
2
HIGH PERFORMANCE E CMOS TECHNOLOGY
fmax = 125 MHz Maximum Operating Frequency
tpd = 7.5 ns Propagation Delay
Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns,
tsu3 (CLK2/3) = 3.5ns
TTL/3.3V/2.5V Compatible Input Thresholds and
Generic Generic
Output Levels
Logic Block Logic Block
Electrically Erasable and Reprogrammable
Input Bus Input Bus
Non-Volatile
Programmable Speed/Power Logic Path Optimization
IN-SYSTEM PROGRAMMABLE
ispLSI 5000V Description
Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
The ispLSI 5000V Family of In-System Programmable
Reprogram Soldered Devices for Faster Debugging
High Density Logic Devices is based on Generic Logic
100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
Blocks (GLBs) of 32 registered macrocells and a single
3.3V IN-SYSTEM PROGRAMMABLE
Global Routing Pool (GRP) structure interconnecting the
ARCHITECTURE FEATURES
GLBs.
Enhanced Pin-Locking Architecture with Single-
Level Global Routing Pool and SuperWIDE GLBs
Outputs from the GLBs drive the Global Routing Pool
Wrap Around Product Term Sharing Array Supports
(GRP) between the GLBs. Switching resources are pro-
up to 35 Product Terms Per Macrocell
vided to allow signals in the Global Routing Pool to drive
Macrocells Support Concurrent Combinatorial and
Registered Functions any or all the GLBs in the device. This mechanism allows
Macrocell Registers Feature Multiple Control
fast, efficient connections across the entire device.
Options Including Set, Reset and Clock Enable
Four Dedicated Clock Input Pins Plus Macrocell
Each GLB contains 32 macrocells and a fully populated,
Product Term Clocks
programmable AND-array with 160 logic product terms
Slew and Skew Programmable I/O (SASPI/O)
and five extra control product terms. The GLB has 68
Supports Programmable Bus Hold, Pull-up, Open
inputs from the Global Routing Pool which are available
Drain and Slew and Skew Rate Options
in both true and complement form for every product term.
Six Global Output Enable Terms, Two Global OE
The 160 product terms are grouped in 32 sets of five and
Pins and One Product Term OE per Macrocell
PC and UNIX Platforms sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 35 product terms for
a single function. Alternatively, the PTSA can be by-
passed for functions of five product terms or less. The
Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; Input Bus Input Bus
Generic
Generic
Logic Block Logic Block
Specifications ispLSI 5256VA
Functional Block Diagram
Figure 1. ispLSI 5256VA Functional Block Diagram (272 BGA Option)
Input Bus Input Bus
TDI
Boundary
Scan TDO
Generic Generic
Interface
VCCIO Logic Block
Logic Block
1
I/O 0 / TOE
I/O 143
I/O 1
I/O 142
I/O 2
I/O 141
I/O 3
I/O 140
I/O 20 I/O 123
I/O 21 I/O 122
I/O 22 I/O 121
I/O 23 I/O 120
Global Routing Pool
I/O 119
I/O 24
(GRP) I/O 118
I/O 25
I/O 117
I/O 26
I/O 116
I/O 27
I/O 99
I/O 44
I/O 98
I/O 45
I/O 97
I/O 46
I/O 96
I/O 47
Generic Generic
Logic Block Logic Block
Input Bus Input Bus
GSET/GRST
1. CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Which I/O is multiplexed is
determined by the package type used (see table below).
Package Type Multplexed Signals
208 PQFP I/O 89 / CLK2 I/O 98 / CLK3 I/O 0 / TOE
208 fpBGA I/O 89 / CLK2 I/O 98 / CLK3 I/O 0 / TOE
272 BGA I/O 119 / CLK2 I/O 131 / CLK3 I/O 0 / TOE
2
GOE0
Input Bus Input Bus
GOE1
Generic Generic
Logic Block Logic Block
I/O 48
I/O 191
I/O 49
I/O 190
I/O 50
I/O 189
I/O 51
I/O 188
I/O 68
I/O 171
I/O 69
I/O 170
I/O 70
I/O 169
I/O 71
I/O 168
I/O 72
I/O 167
I/O 73
I/O 166
I/O 74
I/O 165
I/O 75
I/O 164
I/O 92
I/O 147
I/O 93
I/O 146
I/O 94
I/O 145
I/O 95
I/O 144
CLK 0
CLK 1
TCK
1
CLK 2
1
CLK 3
TMS