Input Bus Input Bus Input Bus Input Bus Generic Generic Generic Generic Logic Block Logic Block Logic Block Logic Block ispLSI 5512VA In-System Programmable 3.3V SuperWIDE High Density PLD Features Functional Block Diagram SuperWIDE HIGH-DENSITY IN-SYSTEM Input Bus Input Bus Input Bus Input Bus PROGRAMMABLE LOGIC Boundary Scan Generic Generic Generic Generic 3.3V Power Supply Interface Logic Block Logic Block Logic Block Logic Block User Selectable 3.3V/2.5V I/O 24000 PLD Gates / 512 Macrocells Up to 288 I/O Pins 512 Registers High-Speed Global Interconnect SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. Global Routing Pool PCB Efficient Ball Grid Array (BGA) Package Options (GRP) Interfaces with Standard 5V TTL Devices 2 HIGH PERFORMANCE E CMOS TECHNOLOGY fmax = 110 MHz Maximum Operating Frequency tpd = 8.5 ns Propagation Delay Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns, tsu3 (CLK2/3) = 3.5ns TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels Generic Generic Generic Generic Electrically Erasable and Reprogrammable Logic Block Logic Block Logic Block Logic Block Non-Volatile Input Bus Input Bus Input Bus Input Bus Programmable Speed/Power Logic Path Optimization IN-SYSTEM PROGRAMMABLE ispLSI 5000V Description Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality The ispLSI 5000V Family of In-System Programmable Reprogram Soldered Devices for Faster Debugging High Density Logic Devices is based on Generic Logic 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND Blocks (GLBs) of 32 registered macrocells and a single 3.3V IN-SYSTEM PROGRAMMABLE Global Routing Pool (GRP) structure interconnecting the ARCHITECTURE FEATURES GLBs. Enhanced Pin-Locking Architecture with Single- Level Global Routing Pool and SuperWIDE GLBs Outputs from the GLBs drive the Global Routing Pool Wrap Around Product Term Sharing Array Supports (GRP) between the GLBs. Switching resources are pro- up to 35 Product Terms Per Macrocell vided to allow signals in the Global Routing Pool to drive Macrocells Support Concurrent Combinatorial and Registered Functions any or all the GLBs in the device. This mechanism allows Macrocell Registers Feature Multiple Control fast, efficient connections across the entire device. Options Including Set, Reset and Clock Enable Four Dedicated Clock Input Pins Plus Macrocell Each GLB contains 32 macrocells and a fully populated, Product Term Clocks programmable AND-array with 160 logic product terms Slew and Skew Programmable I/O (SASPI/O) and five extra control product terms. The GLB has 68 Supports Programmable Bus Hold, Pull-up, Open inputs from the Global Routing Pool which are available Drain and Slew and Skew Rate Options in both true and complement form for every product term. Six Global Output Enable Terms, Two Global OE The 160 product terms are grouped in 32 sets of five and Pins and One Product Term OE per Macrocell sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be by- passed for functions of five product terms or less. The Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Input Bus Input Bus Input Bus Input Bus Generic Generic Generic Generic Logic Block Logic Block Logic Block Logic Block Specifications ispLSI 5512VA Functional Block Diagram Figure 1. ispLSI 5512VA Functional Block Diagram (388 BGA Option) Input Bus Input Bus Input Bus Input Bus TDI Boundary Scan TDO Generic Generic Generic Generic Interface VCCIO Logic Block Logic Block Logic Block Logic Block 1 I/O 0 / TOE I/O 215 I/O 1 I/O 214 I/O 2 I/O 213 I/O 3 I/O 212 I/O 14 I/O 201 I/O 15 I/O 200 I/O 16 I/O 199 I/O 17 I/O 198 I/O 18 I/O 197/CLK3 I/O 19 I/O 196 I/O 20 I/O 195 I/O 21 I/O 194 I/O 32 I/O 183 I/O 33 I/O 182 I/O 34 I/O 181 I/O 35 I/O 180 Global Routing Pool I/O 36 I/O 179/CLK2 (GRP) I/O 37 I/O 178 I/O 177 I/O 38 I/O 176 I/O 39 I/O 50 I/O 165 I/O 51 I/O 164 I/O 52 I/O 163 I/O 53 I/O 162 I/O 54 I/O 161 I/O 55 I/O 160 I/O 159 I/O 56 I/O 158 I/O 57 I/O 147 I/O 68 I/O 146 I/O 69 I/O 70 I/O 145 I/O 71 I/O 144 Generic Generic Generic Generic Logic Block Logic Block Logic Block Logic Block Input Bus Input Bus Input Bus Input Bus GSET/GRST 1. CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Which I/O is multiplexed is determined by the package type used see table below. Package Type Multiplexed Signals 388 BGA I/O 179 / CLK2 I/O 197 / CLK3 I/O 0 / TOE 272 BGA I/O 119 / CLK2 I/O 131 / CLK 3 I/O 0 / TOE 208 PQFP I/O 89 / CLK2 I/O 98 / CLK 3 I/O 0 / TOE 2 GOE0 Input Bus Input Bus Input Bus Input Bus GOE1 Generic Generic Generic Generic Logic Block Logic Block Logic Block Logic Block I/O 72 I/O 287 I/O 73 I/O 286 I/O 74 I/O 285 I/O 75 I/O 284 I/O 86 I/O 273 I/O 87 I/O 272 I/O 88 I/O 271 I/O 89 I/O 270 I/O 90 I/O 269 I/O 91 I/O 268 I/O 92 I/O 267 I/O 93 I/O 266 I/O 104 I/O 255 I/O 105 I/O 254 I/O 106 I/O 253 I/O 107 I/O 252 I/O 108 I/O 251 I/O 109 I/O 250 I/O 110 I/O 249 I/O 111 I/O 248 I/O 122 I/O 237 I/O 123 I/O 236 I/O 124 I/O 235 I/O 125 I/O 234 I/O 126 I/O 233 I/O 127 I/O 232 I/O 128 I/O 231 I/O 129 I/O 230 I/O 140 I/O 219 I/O 141 I/O 218 I/O 142 I/O 217 I/O 143 I/O 216 CLK 0 CLK 1 TCK 1 CLK 2 1 CLK 3 TMS