Input Bus Input Bus Input Bus Input Bus Generic Generic Generic Generic Logic Block Logic Block Logic Block Logic Block ispLSI 5512VE In-System Programmable 3.3V SuperWIDE High Density PLD Features Functional Block Diagram Second Generation SuperWIDE HIGH DENSITY Input Bus Input Bus Input Bus Input Bus Boundary IN-SYSTEM PROGRAMMABLE LOGIC DEVICE Scan Generic Generic Generic Generic Interface Logic Block Logic Block Logic Block Logic Block 3.3V Power Supply User Selectable 3.3V/2.5V I/O 24000 PLD Gates / 512 Macrocells Up to 256 I/O Pins 512 Registers High-Speed Global Interconnect SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance SuperWIDE Input Gating (68 Inputs) for Fast Global Routing Pool Counters, State Machines, Address Decoders, etc. (GRP) PCB Efficient Ball Grid Array (BGA) Package Options Interfaces with Standard 5V TTL Devices 2 HIGH PERFORMANCE E CMOS TECHNOLOGY fmax = 155 MHz Maximum Operating Frequency tpd = 6.5 ns Propagation Delay TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels Electrically Erasable and Reprogrammable Non-Volatile Generic Generic Generic Generic Logic Block Logic Block Logic Block Logic Block Programmable Speed/Power Logic Path Optimization Input Bus Input Bus Input Bus Input Bus IN-SYSTEM PROGRAMMABLE Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality ispLSI 5000VE Description Reprogram Soldered Devices for Faster Debugging The ispLSI 5000VE Family of In-System Programmable 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND High Density Logic Devices is based on Generic Logic 3.3V IN-SYSTEM PROGRAMMABLE Blocks (GLBs) of 32 registered macrocells and a single ARCHITECTURE FEATURES Global Routing Pool (GRP) structure interconnecting the Enhanced Pin-Locking Architecture with Single- GLBs. Level Global Routing Pool and SuperWIDE GLBs Wrap Around Product Term Sharing Array Supports Outputs from the GLBs drive the Global Routing Pool up to 35 Product Terms Per Macrocell (GRP) between the GLBs. Switching resources are pro- Macrocells Support Concurrent Combinatorial and Registered Functions vided to allow signals in the Global Routing Pool to drive Macrocell Registers Feature Multiple Control any or all the GLBs in the device. This mechanism allows Options Including Set, Reset and Clock Enable fast, efficient connections across the entire device. Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks Each GLB contains 32 macrocells and a fully populated, Programmable I/O Supports Programmable Bus programmable AND-array with 160 logic product terms Hold, Pull-up, Open Drain and Slew Rate Options and three extra control product terms. The GLB has 68 Four Global Product Term Output Enables, Two inputs from the Global Routing Pool which are available Global OE Pins and One Product Term OE per in both true and complement form for every product term. Macrocell The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be by- passed for functions of five product terms or less. The three extra product terms are used for shared controls: reset, clock, clock enable and output enable. Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Input Bus Input Bus Input Bus Input Bus Generic Generic Generic Generic Logic Block Logic Block Logic Block Logic Block Specifications ispLSI 5512VE Functional Block Diagram Figure 1. ispLSI 5512VE Functional Block Diagram (256-I/O Option) Input Bus Input Bus Input Bus Input Bus TDI Boundary Scan TDO Generic Generic Generic Generic Interface VCCIO Logic Block Logic Block Logic Block Logic Block 1 TOE I/O 191 I/O 1 I/O 190 I/O 2 I/O 189 I/O 3 I/O 188 I/O 12 I/O 179 I/O 13 I/O 178 I/O 14 I/O 177 I/O 15 I/O 176 I/O 16 I/O 175/CLK3 I/O 17 I/O 174 I/O 18 I/O 173 I/O 19 I/O 172 I/O 28 I/O 163 I/O 29 I/O 162 I/O 30 I/O 161 I/O 31 I/O 160 Global Routing Pool I/O 32 (GRP) I/O 159/CLK2 I/O 33 I/O 158 I/O 34 I/O 157 I/O 156 I/O 35 I/O 44 I/O 147 I/O 45 I/O 146 I/O 145 I/O 46 I/O 144 I/O 47 I/O 143 I/O 48 I/O 49 I/O 142 I/O 141 I/O 50 I/O 140 I/O 51 I/O 60 I/O 131 I/O 130 I/O 61 I/O 129 I/O 62 I/O 128 I/O 63 Generic Generic Generic Generic Logic Block Logic Block Logic Block Logic Block Input Bus Input Bus Input Bus Input Bus RESET 1. CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Use the table below to determine which I/O is shared by package type. Package Type Multiplexed Signals 256 fpBGA I/O 119 / CLK2 I/O 131 / CLK3 I/O 0 / TOE 272 BGA I/O 119 / CLK2 I/O 131 / CLK 3 I/O 0 / TOE 388 fpBGA I/O 179 / CLK2 I/O 197 / CLK 3 I/O 0 / TOE 388 BGA I/O 179 / CLK2 I/O 197 / CLK 3 I/O 0 / TOE 2 GOE0 Input Bus Input Bus Input Bus Input Bus GOE1 Generic Generic Generic Generic Logic Block Logic Block Logic Block Logic Block I/O 64 I/O 255 I/O 65 I/O 254 I/O 66 I/O 253 I/O 67 I/O 252 I/O 76 I/O 243 I/O 77 I/O 242 I/O 78 I/O 241 I/O 79 I/O 240 I/O 80 I/O 239 I/O 81 I/O 238 I/O 82 I/O 237 I/O 83 I/O 236 I/O 92 I/O 227 I/O 93 I/O 226 I/O 94 I/O 225 I/O 95 I/O 224 I/O 96 I/O 223 I/O 97 I/O 222 I/O 98 I/O 221 I/O 99 I/O 220 I/O 108 I/O 211 I/O 109 I/O 210 I/O 110 I/O 209 I/O 111 I/O 208 I/O 112 I/O 207 I/O 113 I/O 206 I/O 114 I/O 205 I/O 115 I/O 204 I/O 124 I/O 195 I/O 125 I/O 194 I/O 126 I/O 193 I/O 127 I/O 192 CLK 0 CLK 1 TCK 1 CLK 2 1 CLK 3 TMS