ispPAC-POWR1014-02TN48I Lattice

ispPAC-POWR1014/A In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller November 2015 Data Sheet DS1014 Features Application Block Diagram Monitor and Control Multiple Power Supplies Primary Simultaneously monitors up to 10 power Supply 3.3 V supplies Primary Provides up to 14 output control signals Supply Programmable digital and analog circuitry 2.5 V Primary Embedded PLD for Sequence Control Supply 1.8 V 24-macrocell CPLD implements both state machines and combinatorial logic functions Primary Supply POL 1 Embedded Programmable Timers Four independent timers 32s to 2 second intervals for timing sequences Primary Supply Analog Input Monitoring POL N 10 independent analog monitor inputs Other Control/Supervisory Two programmable threshold comparators per Signals analog input 12 Digital 2 MOSFET Hardware window comparison Outputs Drivers 2 10-bit ADC for I C monitoring (ispPAC- CPLD POWR1014A only) 24 Macrocells 53 Inputs High-Voltage FET Drivers ADC* 2 I C Power supply ramp up/down control Bus* 2 4 Digital I C 4 Timers CPU Programmable current and voltage output Inputs Interface ispPAC-POWR1014A Independently configurable for FET control or *ispPAC-POWR1014A only. digital output 2 Description 2-Wire (I C/SMBus Compatible) Interface Comparator status monitor Lattices Power Manager II ispPAC-POWR1014/A is a ADC readout general-purpose power-supply monitor and sequence Direct control of inputs and outputs controller, incorporating both in-system programmable Power sequence control logic and in-system programmable analog functions Only available with ispPAC-POWR1014A 2 implemented in non-volatile E CMOS technology. The ispPAC-POWR1014/A device provides 10 independent 3.3 V Operation, Wide Supply Range 2.8 V to 3.96 V analog input channels to monitor up to 10 power supply Industrial temperature range: 40C to +85C test points. Each of these input channels has two inde- 48-pin TQFP package, lead-free option pendently programmable comparators to support both high/low and in-bounds/out-of-bounds (window-com- Multi-Function JTAG Interface pare) monitor functions. Four general-purpose digital In-system programming 2 inputs are also provided for miscellaneous control func- Access to all I C registers tions. Direct input control The ispPAC-POWR1014/A provides 14 open-drain digi- tal outputs that can be used for controlling DC-DC con- verters, low-drop-out regulators (LDOs) and opto- couplers, as well as for supervisory and general-pur- pose logic interface functions. Two of these outputs (HVOUT1-HVOUT2) may be configured as high-voltage 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1014 2.2 10 Analog Inputs and Voltage Monitors Enables Voltage Monitoring Other Board Circuitry Digital Monitoring GNDD (2) 2 FET 12 OPEN-DRAIN DRIVERS DIGITAL OUTPUTS GNDA OUTPUT ROUTING SDA* POOL SCL* RESETb PLDCLK MCLK ATDI TDI TDISEL TCK TMS TDO VCCJ APS VCCA VCCD (2) 10 ANALOG INPUTS 4 DIGITAL VCCINP AND VOLTAGE MONITORS INPUTS ispPAC-POWR1014/A Data Sheet MOSFET drivers. In high-voltage mode these outputs can provide up to 12 V for driving the gates of n-channel MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down. The ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32 s to 2 seconds. The CPLD is programmed using Logi- Builder, an easy-to-learn language integrated into the PAC-Designer software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs. 2 The on-chip 10-bit A/D converter is used to monitor the V voltage through the I C bus or JTAG interface of the MON ispPAC-POWR1014A device. 2 The I C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V MON inputs, read back the status of each of the V comparator and PLD outputs, control logic signals IN2 to IN4 and MON 2 control the output pins (ispPAC-POWR1014A only). The JTAG interface can be used to read out all I C registers during manufacturing. Figure 1. ispPAC-POWR1014/A Block Diagram MEASUREMENT ADC* CONTROL LOGIC* VMON1 VMON2 VMON3 HVOUT1 VMON4 HVOUT2 VMON5 VMON6 VMON7 VMON8 VMON9 CPLD VMON10 OUT3/(SMBA*) 24 MACROCELLS OUT4 OUT5 53 INPUTS OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 IN1 OUT13 IN2 2 OUT14 CLOCK TIMERS I C IN3 JTAG LOGIC OSCILLATOR (4) INTERFACE IN4 *ispPAC-POWR1014A only. 2