ispPAC-POWR604 In-System Programmable Power Supply Sequencing Controller and Monitor August 2004 Data Sheet Features Application Block Diagram Monitor and Control Multiple Power Voltage Monitor 6 Voltage Monitor 5 Supplies Simultaneously monitors and sequences up to six 2.5-5V Supply power supplies Sequence controller for power-up conditions 1.0uF 0.1uF 6 Analog Inputs Provides four output control signals Digital Logic VDD VDDINP Programmable digital and analog circuitry VMON1 CPU/ASIC CPU RESETN VMON2 OUT5 BROWNOUT INT Card etc. VMON3 OUT6 LOAD ENABLE VMON4 Embedded PLD for Sequence Control OUT7 POWER OK VMON5 OUT8 VMON6 Implements state machine and input conditional V ispPAC-POWR604 DD Comp1 events Power Sequence Comp2 CLK Comp3 Controller Comp4 In-System Programmable (ISP) through JTAG RESET Comp5 2 Comp6 and on-chip E CMOS POR CARD RESETN IN1 WDT IN Embedded Programmable Timers IN2 INT ACK CREF IN3 Two Programmable 8-bit timers (32s to 524ms) DONE 0.1uF IN4 Programmable time delay for pulse stretching or other power supply management Analog Comparators for Monitoring Description Six analog comparators for monitoring The Lattice ispPAC -POWR604 incorporates both in- 192 precise programmable threshold levels system programmable logic and in-system programma- spanning 1.03V to 5.72V ble analog circuits to perform special functions for Each comparator can be independently cong- power supply sequencing and monitoring. The ispPAC- ured around standard logic supply voltages of POWR604 device has the capability to be congured 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V through software to control up to four outputs for power Other user-dened voltages possible supply sequencing and six comparators monitoring sup- Six direct comparator outputs ply voltage limits, along with four digital inputs for inter- Embedded Oscillator facing to other control circuits or digital logic. Once Built-in clock generator, 250kHz congured, the design is downloaded into the device Programmable clock frequency through a standard JTAG interface. The circuit congu- 2 Programmable timer pre-scaler ration and routing are stored in non-volatile E CMOS. External clock support PAC-Designer, an easy-to-use Windows-compatible software package, gives users the ability to design the Programmable Open-Drain Outputs logic and sequences that control the power supplies or Four digital outputs for logic and power supply regulator circuits. The user has control over timing func- control tions, programmable logic functions and comparator Expandable with ispMACH 4000 CPLD threshold values as well as I/O congurations. 2.25V to 5.5V Supply Range In-system programmable at 3.0V to 5.5V Industrial temperature range: -40C to +85C Automotive temperature range: -40C to +125C 44-pin TQFP package Lead-free package option 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice. www.latticesemi.com 1 pwr604 02.1 Lattice Semiconductor ispPAC-POWR604 Data Sheet Power Supply Sequence Controller and Monitor The ispPAC-POWR604 device is specically designed as a fully-programmable power supply sequencing controller and monitor for managing up to four separate power supplies, as well as monitoring up to six analog inputs or sup- plies. The ispPAC-POWR604 device contains an internal PLD that is programmable by the user to implement digi- tal logic functions and control state machines. The internal PLD connects to two programmable timers, special purpose I/O and the programmable monitoring circuit blocks. The internal PLD and timers can be clocked by either an internal programmable clock oscillator or an external clock source. The voltage monitors are arranged as six independent comparators each with 192 programmable trip point set- tings. Monitoring levels are set around the following standard voltages: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V or 5.0V. All six voltages can be monitored simultaneously (i.e., continuous-time operation). Other non-standard voltage lev- els can be accounted for using various scale factors. For added robustness, the comparators feature a variable hysteresis that scales with the voltage they monitor. Generally, a larger hysteresis is better. However, as power supply voltages get smaller, that hysteresis increasingly affects trip-point accuracy. Therefore, the hysteresis is +/-16mV for 5V supplies and scales down to +/-3mV for 1.2V supplies, or about 0.3% of the trip point. The programmable logic functions consist of a block of 20 inputs with 41 product terms and eight macrocells. The architecture supports the sharing of product terms to enhance the overall usability. The four output pins are open-drain outputs. These outputs can be used to drive enable lines for DC/DC converters or other control logic associated with power supply control. The four outputs are driven from the macrocells. Figure 1. ispPAC-POWR604 Block Diagram ispPAC-POWR604 6 COMP1 COMP2 VMON1 COMP3 VMON2 Comparator COMP4 VMON3 Sequence Analog COMP5 Outputs VMON4 Controller Inputs COMP6 VMON5 CPLD 6 VMON6 20 I/P & 8 Macrocell GLB IN1 5 4 OUT5 IN2 Logic Digital OUT6 IN3 250kHz OUT7 Inputs Outputs IN4 Internal OUT8 RESET OSC 2 Timers CLKIO 2