TM ProcessorPM-POWR605 In-System Programmable Power Supply Supervisor, Reset Generator and Watchdog Timer April 2015 Data Sheet DS1034 Features Application Block Diagram Precision Programmable Threshold Input Power Supply Monitors, Threshold Accuracy 0.7% Simultaneously monitors up to six power supplies DC-DC DC-DC DC-DC Programmable analog trip points (1% step size 1 2 n 192 steps) Manual Programmable glitch filter Reset In Power-off detection (75 mV) Power Supply Embedded Programmable Timers Bus Four independent timers 32 s to 2 second intervals for timing sequences Voltage Supervisor Interrupt Embedded PLD for Logical Control Power Fail Rugged 16-macrocell CPLD architecture Reset Generator CPU Reset in 81 product terms / 28 inputs Implements state machines and combinatorial WDT Trigger functions Watchdog Timer Interrupt WDT Power-Down Mode I < 10 A CC Digital I/O Power Down CPU / Two dedicated digital inputs uProcessor ProcessorPM- Five programmable digital I/O pins POWR605 Wide Supply Range (2.64 V to 3.96 V) Power Up/Down Control In-system programmable through JTAG Industrial temperature range: 40 C to +105 C 24-pin QFN package, lead-free option The diagram above shows how a ProcessorPM- POWR605 is used in a typical application. It controls Description power to the microprocessor system, generates the Lattices Power Manager II ProcessorPM-POWR605 is CPU reset and monitors critical power supply voltages, a general-purpose power-supply monitor, reset genera- generating interrupts whenever faults are detected. It tor and watchdog timer, incorporating both in-system also provides a watchdog timer function to detect CPU programmable logic and analog functions implemented operating and bus timeout errors. 2 in non-volatile E CMOS technology. The Proces- The ProcessorPM-POWR605 incorporates a 16-macro- sorPM-POWR605 device provides six independent ana- cell CPLD. Figure 1 shows the analog input compara- log input channels to monitor power supply voltages. tors and digital inputs used as inputs to the CPLD array. Two general-purpose digital inputs are also provided for The digital output pins providing the external control sig- miscellaneous control functions. nals are driven by the CPLD. Four independently pro- The ProcessorPM-POWR605 provides up to five open grammable timers also interface with the CPLD and can drain digital outputs that can be used for controlling DC- create delays and time-outs ranging from 32 s to 2 DC converters, low-drop-out regulators (LDOs) and opt- seconds. The CPLD is programmed using Logi- ocouplers, as well as for supervisory and general-pur- Builder, an easy-to-learn language integrated into the pose logic interface functions. The five digital, open PAC-Designer software. Control sequences are written drain outputs can optionally be configured as digital to monitor the status of any of the analog input channel inputs to sense more input signals as needed, such as comparators or the digital inputs. manual reset, etc. 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1034 2.0TMS TCK TDI TDO VCCJ GND ProcessorPM-POWR605 Data Sheet Figure 1. ProcessorPM-POWR605 Block Diagram VCC ProcessorPM-POWR605 Power Down Logic IN1 PWRDN IN2 IN OUT1 PLD VMON1 IN OUT2 16 Macrocells VMON2 IN OUT3 VMON3 28 Inputs IN OUT4 VMON4 IN OUT5 VMON5 VMON6 4 Timers JTAG Interface Pin Descriptions Number Name Pin Type Voltage Range Description 1 8, 9 GND Ground Ground Ground 9, 10 Digital Input PLD Input 3 20 IN OUT1 0 V to 5.5 V 2 Open Drain Output Open Drain Output 3 9, 10 Digital Input PLD Input 4 19 IN OUT2 0 V to 5.5 V 2 Open Drain Output Open Drain Output 4 9, 10 Digital Input PLD Input 5 18 IN OUT3 0 V to 5.5 V 2 Open Drain Output Open Drain Output 5 9, 10 Digital Input PLD Input 6 17 IN OUT4 0 V to 5.5 V 2 Open Drain Output Open Drain Output 6 9, 10 Digital Input PLD Input 7 15 IN OUT5 0 V to 5.5 V 2 Open Drain Output Open Drain Output 7 4, 5 PLD Logic Input 1. When not used, this pin 10 3 22 IN1 PWRDN Digital Input 0 V to 5.5 V should be pulled down with a 10k resistor. IN2 PLD Logic Input 2. When not used, this pin 10 3 21 Digital Input 0 V to 5.5 V should be tied to GND. 12 TCK Digital Input 0 V to 5.5 V JTAG Test Clock Input 13 TDI Digital Input 0 V to 5.5 V JTAG Test Data In - Internal Pull-up 11 TDO Digital Output 0 V to 5.5 V JTAG Test Data Out 14 TMS Digital Input 0 V to 5.5 V JTAG Test Mode Select - Internal Pull-up 6 3, 16 VCC Power 2.64 V to 3.96 V Power Supply 7 10 VCCJ Power 2.25 V to 3.6 V VCC for JTAG Logic Interface Pins 8 1 VMON1 Analog Input 0.3 V to 5.9 V Voltage Monitor Input 1 8 2 VMON2 Analog Input 0.3 V to 5.9 V Voltage Monitor Input 2 2 6 Analog Voltage Monitor Inputs