ispPAC-POWR607 In-System Programmable Power Supply Supervisor, Reset Generator and Watchdog Timer April 2015 Data Sheet DS1011 Features Application Block Diagram Power-Down Mode I < 10 A Input Power Supply CC Programmable Threshold Monitors On/Off Simultaneously monitors up to six power supplies DC-DC DC-DC DC-DC Programmable analog trip points (1% step size 1 2 n Manual 192 steps) Reset In Programmable glitch filter Power Power-off detection (75 mV) Supply Bus Embedded Programmable Timers MOSFET Drivers (2) Four independent timers 32 s to 2 second intervals for timing sequences Voltage Supervisor Interrupt Embedded PLD for Logical Control Power Fail Rugged 16-macrocell CPLD architecture Reset Generator CPU Reset in 81 product terms / 28 inputs Implements state machines and combinatorial WDT Trigger functions Watchdog Timer Interrupt WDT Digital I/O Two dedicated digital inputs Power Down CPU / uProcessor Five programmable digital I/O pins ispPAC-POWR607 Two High-Voltage FET Drivers Power supply ramp up/down control Power Up/Down Control Independently configurable for FET control or digital output (HVOUT1-HVOUT2) can be configured as high-voltage Wide Supply Range (2.64 V to 3.96 V) MOSFET drivers. In high-voltage mode these outputs In-system programmable through JTAG provide 9V for driving the gates of n-channel MOSFETs Industrial temperature range: 40 C to +105 C used as high-side power switches to control power sup- 24-pin and 32-pin QFNS packages, lead-free ply ramp up and ramp down rate. The remaining five option digital, open drain outputs can optionally be configured as digital inputs to sense more input signals as needed, Description such as manual reset, etc. The Power Manager II ispPAC-POWR607 is a general- purpose power-supply monitor, reset generator and The diagram above shows how a ispPAC-POWR607 is watchdog timer, incorporating both in-system program- used in a typical application. It controls power to the mable logic and analog functions implemented in non- microprocessor system, generates the CPU reset and 2 volatile E CMOS technology. The ispPAC-POWR607 monitors critical power supply voltages, generating device provides six independent analog input channels interrupts whenever faults are detected. It also provides to monitor power supply voltages. Two general-purpose a watchdog timer function to detect CPU operating and digital inputs are also provided for miscellaneous control bus timeout errors. functions. The ispPAC-POWR607 incorporates a 16-macrocell The ispPAC-POWR607 provides up to seven open-drain CPLD. Figure 1 shows the analog input comparators digital outputs that can be used for controlling DC-DC and digital inputs used as inputs to the CPLD array. The converters, low-drop-out regulators (LDOs) and opto- digital output pins providing the external control signals couplers, as well as for supervisory and general-pur- are driven by the CPLD. Four independently program- pose logic interface functions. Two of these outputs 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1011 2.0TMS TCK TDI TDO VCCJ GND ispPAC-POWR607 Data Sheet mable timers also interface with the CPLD and can create delays and time-outs ranging from 32s to 2 seconds. The CPLD is programmed using LogiBuilder, an easy-to-learn language integrated into the PAC-Designer soft- ware. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs. Figure 1. ispPAC-POWR607 Block Diagram VCC ispPAC-POWR607 Power Down Logic IN1 PWRDN HVOUT1 IN2 HVOUT2 PLD VMON1 IN OUT3 16 Macrocells VMON2 IN OUT4 VMON3 IN OUT5 28 Inputs VMON4 IN OUT6 VMON5 IN OUT7 VMON6 4 Timers JTAG Interface Pin Descriptions 24-Pin QFNS 32-Pin QFNS Pin Number Pin Number Pin Name Pin Type Voltage Range Description 1 8, 9 11, 12 GND Ground Ground Ground 2 Open Drain Output 0 V to 10 V Open-Drain Output 1 23 30 HVOUT1 FET Gate Driver 0 V to 9 V High-voltage FET Gate Driver 1 2 Open Drain Output 0 V to 10 V Open-Drain Output 2 24 31 HVOUT2 FET Gate Driver 0 V to 9 V High-voltage FET Gate Driver 2 9 Digital Input PLD Input 3 20 27 IN OUT3 0 V to 5.5 V 2 Open Drain Output Open Drain Output 3 9 Digital Input PLD Input 4 19 26 IN OUT4 0 V to 5.5 V 2 Open Drain Output Open Drain Output 4 9 Digital Input PLD Input 5 18 23 IN OUT5 0 V to 5.5 V 2 Open Drain Output Open Drain Output 5 9 Digital Input PLD Input 6 17 22 IN OUT6 0 V to 5.5 V 2 Open Drain Output Open Drain Output 6 9 Digital Input PLD Input 7 15 20 IN OUT7 0 V to 5.5 V 2 Open Drain Output Open Drain Output 7 4, 5 PLD Logic Input 1. When not used, 10 3 Digital Input 0 V to 5.5 V 22 29 IN1 PWRDN this pin should be pulled down with a 10 k resistor. 2 6 Analog Voltage Monitor Inputs