LA4128V-75TN100E Lattice

LA-ispMACH 4000V/Z Automotive Family 3.3 V/1.8 V In-System Programmable SuperFAST High Density PLDs Data Sheet FPGA-DS-02021 Version 2.6 September 2017 LA-ispMACH 4000V/Z Automotive Family Data Sheet Contents Acronyms in This Document ................................................................................................................................................. 5 1. Features ........................................................................................................................................................................ 6 2. Introduction .................................................................................................................................................................. 7 3. Overview ....................................................................................................................................................................... 8 4. Architecture .................................................................................................................................................................. 9 Generic Logic Block ............................................................................................................................................. 9 AND Array ............................................................................................................................................................ 9 Enhanced Logic Allocator .................................................................................................................................. 10 Product Term Allocator ...................................................................................................................................... 11 Cluster Allocator ................................................................................................................................................ 11 Wide Steering Logic ........................................................................................................................................... 11 Macrocell ........................................................................................................................................................... 12 Enhanced Clock Multiplexer .............................................................................................................................. 12 Clock Enable Multiplexer ................................................................................................................................... 13 Initialization Control .......................................................................................................................................... 13 GLB Clock Generator ......................................................................................................................................... 13 Output Routing Pool (ORP) ............................................................................................................................... 14 Output Routing Multiplexers ............................................................................................................................. 14 ORP Bypass and Fast Output Multiplexers ........................................................................................................ 15 Output Enable Routing Multiplexers ................................................................................................................. 15 5. I/O Cell ........................................................................................................................................................................ 16 6. Global OE Generation ................................................................................................................................................. 17 7. Zero Power/Low Power and Power Management ...................................................................................................... 18 8. IEEE 1149.1-Compliant Boundary Scan Testability ..................................................................................................... 19 9. I/O Quick Configuration .............................................................................................................................................. 20 10. IEEE 1532-Compliant In-System Programming ....................................................................................................... 21 11. User Electronic Signature ........................................................................................................................................ 22 12. Security Bit .............................................................................................................................................................. 23 13. Hot Socketing .......................................................................................................................................................... 24 14. Density Migration ................................................................................................................................................... 25 15. AEC-Q100 Tested and Qualified .............................................................................................................................. 26 1, 2, 3 16. Absolute Maximum Ratings .............................................................................................................................. 27 17. Recommended Operating Conditions..................................................................................................................... 28 18. Erase Reprogram Specifications.............................................................................................................................. 29 1, 2, 3 19. Hot Socketing Characteristics ........................................................................................................................... 30 20. I/O Recommended Operating Conditions .............................................................................................................. 31 21. DC Electrical Characteristics.................................................................................................................................... 32 22. Supply Current, LA-ispMACH 4000V ........................................................................................................................ 33 23. Supply Current, LA-ispMACH 4000Z ........................................................................................................................ 34 24. I/O DC Electrical Characteristics ............................................................................................................................. 35 25. LA-ispMACH 4000V/Z External Switching Characteristics ...................................................................................... 36 26. Timing Model .......................................................................................................................................................... 37 27. LA-ispMACH 4000V/Z Internal Timing Parameters ................................................................................................. 38 28. LA-ispMACH 4000V/Z Timing Adders...................................................................................................................... 40 29. Boundary Scan Waveforms and Timing Specifications ........................................................................................... 41 30. Power Consumption ............................................................................................................................................... 42 31. Power Estimation Coefficients* .............................................................................................................................. 43 32. Switching Test Conditions ....................................................................................................................................... 44 33. Signal Descriptions .................................................................................................................................................. 45 34. LA-ispMACH 4000V ORP Reference Table ................................................................................................................ 46 35. LA-ispMACH 4000Z ORP Reference Table ................................................................................................................ 47 1 36. LA-ispMACH 4000V/Z Power Supply and NC Connections .................................................................................... 48 2014-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02021-2.6