LA-ispPAC-POWR1014/A Automotive Family In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller September 2013 Data Sheet DS1018 Features Application Block Diagram Monitor and Control Multiple Power Supplies Primary Simultaneously monitors up to 10 power Supply 3.3V supplies Primary Provides up to 14 output control signals Supply Programmable digital and analog circuitry 2.5V Primary AEC-Q100 Tested and Qualified Supply 1.8V Embedded PLD for Sequence Control Primary 24-macrocell CPLD implements both state Supply POL 1 machines and combinatorial logic functions Embedded Programmable Timers Four independent timers Primary 32s to 2 second intervals for timing sequences Supply POL N Analog Input Monitoring Other Control/Supervisory Signals 10 independent analog monitor inputs Two programmable threshold comparators per 12 Digital 2 MOSFET Outputs Drivers analog input Hardware window comparison CPLD 2 10-bit ADC for I C monitoring (LA-ispPAC- 24 Macrocells 53 Inputs POWR1014A only) ADC* 2 I C Bus* High-Voltage FET Drivers 2 4 Digital I C 4 Timers CPU Inputs Interface Power supply ramp up/down control LA-ispPAC-POWR1014A Programmable current and voltage output *LA-ispPAC-POWR1014A only. Independently configurable for FET control or digital output Description 2 2-Wire (I C/SMBus Compatible) Interface Lattices Power Manager II LA-ispPAC-POWR1014/A is Comparator status monitor a general-purpose power-supply monitor and sequence ADC readout controller, incorporating both in-system programmable Direct control of inputs and outputs logic and in-system programmable analog functions 2 Power sequence control implemented in non-volatile E CMOS technology. The Only available with LA-ispPAC-POWR1014A LA-ispPAC-POWR1014/A device provides 10 indepen- dent analog input channels to monitor up to 10 power 3.3V Operation, Wide Supply Range 2.8V to supply test points. Each of these input channels has 3.96V two independently programmable comparators to sup- Automotive temperature range: -40C to +105C port both high/low and in-bounds/out-of-bounds (win- 48-pin TQFP package, lead-free option dow-compare) monitor functions. Four general-purpose Multi-Function JTAG Interface digital inputs are also provided for miscellaneous con- In-system programming trol functions. 2 Access to all I C registers Direct input control The LA-ispPAC-POWR1014/A provides 14 open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and opto- couplers, as well as for supervisory and general-pur- pose logic interface functions. Two of these outputs (HVOUT1-HVOUT2) may be configured as high-voltage 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 DS1018 01.3 10 Analog Inputs and Voltage Monitors Enables Voltage Monitoring Other Board Circuitry Digital Monitoring GNDD (2) 2 F E T 12 O P E N - D R A I N D R I V E R S D I G I T A L O U T P U T S GNDA O U T P U T R O U T I N G SDA (POWR1014A only) P O O L SCL (POWR1014A only) R E S E T b P L D C L K M C L K A T D I T D I TDISEL T C K T M S T D O VCCJ APS VCCA VCCD (2) 1 0 A N A L O G I N P U T S 4 D I G I T A L VCCINP A N D V O L T A G E M O N I T O R S I N P U T S LA-ispPAC-POWR1014/A Automotive Family Data Sheet MOSFET drivers. In high-voltage mode these outputs can provide up to 8V for driving the gates of n-channel MOS- FETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down. The LA-ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32s to 2 seconds. The CPLD is programmed using Logi- Builder, an easy-to-learn language integrated into the PAC-Designer software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs. 2 The on-chip 10-bit A/D converter is used to monitor the V voltage through the I C bus or JTAG interface of the MON LA-ispPAC-POWR1014A device. 2 The I C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V MON inputs, read back the status of each of the V comparator and PLD outputs, control logic signals IN2 to IN4 and MON 2 control the output pins (LA-ispPAC-POWR1014A only). The JTAG interface can be used to read out all I C registers during manufacturing. Figure 5-1. LA-ispPAC-POWR1014/A Block Diagram MEASUREMENT ADC* CONTROL LOGIC* VMON1 VMON2 VMON3 HVOUT1 VMON4 HVOUT2 VMON5 VMON6 VMON7 VMON8 VMON9 CPLD VMON10 OUT3/(SMBA*) 24 MACROCELLS OUT4 OUT5 53 INPUTS OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 IN1 OUT13 IN2 2 OUT14 CLOCK TIMERS I C IN3 JTAG LOGIC OSCILLATOR (4) INTERFACE IN4 *LA-ispPAC-POWR1014A only. 5-2