ispMACH 4000V/B/C/Z Family
3.3V/2.5V/1.8V In-System Programmable
TM
SuperFAST High Density PLDs
June 2014 Data Sheet DS1020
Broad Device Offering
Features
Multiple temperature range support
High Performance
Commercial: 0 to 90C junction (T )
j
f = 400MHz maximum operating frequency
MAX
Industrial: -40 to 105C junction (T )
j
t = 2.5ns propagation delay
PD
Extended: -40 to 130C junction (T )
j
Up to four global clock pins with programmable
For AEC-Q100 compliant devices, refer to
clock polarity control
LA-ispMACH 4000V/Z Automotive Data Sheet
Up to 80 PTs per output
Easy System Integration
Ease of Design
Superior solution for power sensitive consumer
Enhanced macrocells with individual clock,
applications
reset, preset and clock enable controls
Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
Up to four global OE controls
Operation with 3.3V (4000V), 2.5V (4000B) or
Individual local OE control per I/O pin
1.8V (4000C/Z) supplies
TM
Excellent First-Time-Fit and refit
5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
TM
Fast path, SpeedLocking Path, and wide-PT
interfaces
path
Hot-socketing
Wide input gating (36 input logic blocks) for fast
Open-drain capability
counters, state machines and address decoders
Input pull-up, pull-down or bus-keeper
Programmable output slew rate
Zero Power (ispMACH 4000Z) and Low
3.3V PCI compatible
Power (ispMACH 4000V/B/C)
IEEE 1149.1 boundary scan testable
Typical static current 10A (4032Z)
3.3V/2.5V/1.8V In-System Programmable
Typical static current 1.3mA (4000C)
(ISP) using IEEE 1532 compliant interface
1.8V core low dynamic power
I/O pins with fast setup path
ispMACH 4000Z operational down to 1.6V V
CC
Lead-free package options
Table 1. ispMACH 4000V/B/C Family Selection Guide
ispMACH ispMACH ispMACH ispMACH ispMACH ispMACH
4032V/B/C 4064V/B/C 4128V/B/C 4256V/B/C 4384V/B/C 4512V/B/C
Macrocells 32 64 128 256 384 512
I/O + Dedicated Inputs 30+2/32+4 30+2/32+4/ 64+10/92+4/ 64+10/96+14/ 128+4/192+4 128+4/208+4
64+10 96+4 128+4/160+4
t (ns) 2.5 2.5 2.7 3.0 3.5 3.5
PD
t (ns) 1.8 1.8 1.8 2.0 2.0 2.0
S
t (ns) 2.2 2.2 2.7 2.7 2.7 2.7
CO
f (MHz) 400 400 333 322 322 322
MAX
Supply Voltages (V) 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V
4 4
Pins/Package 44 TQFP 44 TQFP
4 4
48 TQFP 48 TQFP
100 TQFP 100 TQFP
100 TQFP
128 TQFP
1
1
144 TQFP
144 TQFP
176 TQFP 176 TQFP
176 TQFP
2
256 ftBGA/ 256 ftBGA/
256 ftBGA /
3 3
2, 3
fpBGA fpBGA
fpBGA
1. 3.3V (4000V) only.
2. 128-I/O and 160-I/O configurations.
3. Use 256 ftBGA package for all new designs. Refer to PCN#14A-07 for 256 fpBGA package discontinuance.
4. 1.0mm thickness.
2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 1 DS1020_23.4Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet
Table 2. ispMACH 4000Z Family Selection Guide
ispMACH 4032ZC ispMACH 4064ZC ispMACH 4128ZC ispMACH 4256ZC
Macrocells 32 64 128 256
I/O + Dedicated Inputs 32+4/32+4 32+4/32+12/ 64+10/96+4 64+10/96+6/
64+10/64+10 128+4
t (ns) 3.5 3.7 4.2 4.5
PD
t (ns) 2.2 2.5 2.7 2.9
S
t (ns) 3.0 3.2 3.5 3.8
CO
f (MHz) 267 250 220 200
MAX
Supply Voltage (V) 1.8 1.8 1.8 1.8
Max. Standby Icc (A) 20 25 35 55
Pins/Package 48 TQFP 48 TQFP
56 csBGA 56 csBGA
100 TQFP 100 TQFP 100 TQFP
132 csBGA 132csBGA 132 csBGA
176 TQFP
ispMACH 4000 Introduction
The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend
of Lattices two most popular architectures: the ispLSI 2000 and ispMACH 4A. Retaining the best of both families,
the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low
power in a flexible CPLD family.
The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-
ity, routing, pin-out retention and density migration.
The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-
binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packages
ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key
parameters.
The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B)
and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH
4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up
resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/
2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary
scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK,
TMS, TDI and TDO are referenced to V (logic core).
CC
Overview
The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected
by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which
contain multiple I/O cells. This architecture is shown in Figure 1.
2