TM ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable TM SuperFAST High Density PLDs Coolest Power February 2006 Data Sheet TM C Broad Device Offering Features Multiple temperature range support High Performance Commercial: 0 to 90C junction (T ) j f = 400MHz maximum operating frequency MAX Industrial: -40 to 105C junction (T ) j t = 2.5ns propagation delay PD Automotive: -40 to 130C junction (T ) j Up to four global clock pins with programmable Easy System Integration clock polarity control Superior solution for power sensitive consumer Up to 80 PTs per output applications Ease of Design Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O Enhanced macrocells with individual clock, Operation with 3.3V (4000V), 2.5V (4000B) or reset, preset and clock enable controls 1.8V (4000C/Z) supplies Up to four global OE controls 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI Individual local OE control per I/O pin interfaces TM Excellent First-Time-Fit and ret Hot-socketing TM Fast path, SpeedLocking Path, and wide-PT Open-drain capability path Input pull-up, pull-down or bus-keeper Wide input gating (36 input logic blocks) for fast Programmable output slew rate counters, state machines and address decoders 3.3V PCI compatible IEEE 1149.1 boundary scan testable Zero Power (ispMACH 4000Z) and Low 3.3V/2.5V/1.8V In-System Programmable Power (ispMACH 4000V/B/C) (ISP) using IEEE 1532 compliant interface Typical static current 10A (4032Z) I/O pins with fast setup path Typical static current 1.3mA (4000C) Lead-free package options 1.8V core low dynamic power ispMACH 4000Z operational down to 1.6V V CC Table 1. ispMACH 4000V/B/C Family Selection Guide ispMACH ispMACH ispMACH ispMACH ispMACH ispMACH 4032V/B/C 4064V/B/C 4128V/B/C 4256V/B/C 4384V/B/C 4512V/B/C Macrocells 32 64 128 256 384 512 I/O + Dedicated 30+2/32+4 30+2/32+4/ 64+10/92+4/ 64+10/96+14/ 128+4/192+4 128+4/208+4 Inputs 64+10 96+4 128+4/160+4 t (ns) 2.5 2.5 2.7 3.0 3.5 3.5 PD t (ns) 1.8 1.8 1.8 2.0 2.0 2.0 S t (ns) 2.2 2.2 2.7 2.7 2.7 2.7 CO f (MHz) 400 400 333 322 322 322 MAX Supply Voltages (V) 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V Pins/Package 44 TQFP 44 TQFP 48 TQFP 48 TQFP 100 TQFP 100 TQFP 100 TQFP 128 TQFP 1 1 144 TQFP 144 TQFP 176 TQFP 176 TQFP 176 TQFP 2 256 fpBGA 256 fpBGA 256 fpBGA 1. 3.3V (4000V) only. 2. 128-I/O and 160-I/O congurations. 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice. www.latticesemi.com 1 ispm4k 22z.2 Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet Table 2. ispMACH 4000Z Family Selection Guide ispMACH 4032ZC ispMACH 4064ZC ispMACH 4128ZC ispMACH 4256ZC Macrocells 32 64 128 256 I/O + Dedicated Inputs 32+4/32+4 32+4/32+12/ 64+10/96+4 64+10/96+6/ 64+10/64+10 128+4 (ns) 3.5 3.7 4.2 4.5 t PD t (ns) 2.2 2.5 2.7 2.9 S (ns) 3.0 3.2 3.5 3.8 t CO (MHz) 267 250 220 200 f MAX Supply Voltage (V) 1.8 1.8 1.8 1.8 Max. Standby Icc (A) 20 25 35 55 Pins/Package 48 TQFP 48 TQFP 56 csBGA 56 csBGA 100 TQFP 100 TQFP 100 TQFP 132 csBGA 132csBGA 132 csBGA 176 TQFP ispMACH 4000 Introduction The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend of Lattices two most popular architectures: the ispLSI 2000 and ispMACH 4A. Retaining the best of both families, the ispMACH 4000 architecture focuses on signicant innovations to combine the highest performance with low power in a exible CPLD family. The ispMACH 4000 combines high speed and low power with the exibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil- ity, routing, pin-out retention and density migration. The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com- binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch BGA (fpBGA) packages ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters. The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B) and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is congured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/ 2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. Overview The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1. 2