TM ispMACH 5000VG Family 3.3V In-System Programmable TM TM SuperBIG, SuperWIDE High Density PLDs December 2001 Data Sheet Ease of Design Features Product term sharing High Density Extensive clocking and OE capability 768 to 1,024 macrocells Easy System Integration 196 to 384 I/Os 3.3V power supply sysCLOCK PLL Timing Control Hot socketing Multiply and divide factors between 1 and 32 Input pull-up, pull-down or bus-keeper Clock shifting capability 3.5ns in 500ps steps Open drain capability Multiple output frequencies Slew rate control External feedback capability for board-level Macrocell-based power management clock deskew IEEE 1149.1 boundary scan testable LVDS/LVPECL clock input capability In-system programmable via IEEE 1532 ISC compliant interface High Speed Logic Implementation SuperWIDE 68-input logic block ispMACH 5000VG Introduction Up to 160 product terms per output Hierarchical routing structure provides fast inter- The ispMACH 5000VG represents the third generation connect of Lattices SuperWIDE CPLD architecture. Through their wide 68-input blocks, these devices give signi- sysIO Capability cantly improved speed performance for typical designs LVCMOS 1.8, 2.5 and 3.3 over architectures with fewer inputs. LVTTL SSTL 2 (I & II) The ispMACH 5000VG takes the unique benets of the SSTL 3 (I & II) SuperWIDE architecture and extends it to higher densi- CTT 3.3, CTT 2.5 ties referred to as SuperBIG, by using the combination HSTL (I & III) of an innovative product term architecture and a two- PCI-X, PCI 3.3 tiered hierarchical routing architecture. Additionally, GTL+ sysCLOCK and sysIO capabilities have been added to AGP-1X maximize system-level performance and integration. 5V tolerance Programmable drive strength Table 1. ispMACH 5000VG Family Selection Guide ispMACH ispMACH 5768VG 51024VG Macrocells 768 1,024 User I/O Options 196/304 304/384 t (ns) 5.0 5.0 PD t Set-up with 0 Hold (ns) 3.0 3.0 S t (ns) 4.4 4.4 CO f (MHz) 178 178 MAX Supply Voltage (V) 3.3V 3.3V Package 256-ball fpBGA 484-ball fpBGA 484-ball fpBGA 676-ball fpBGA www.latticesemi.com 1 5kvg 09 Lattice Semiconductor ispMACH 5000VG Family Data Sheet Figure 1. Functional Block Diagram I/O Bank 0 I/O Bank 3 GLB GLB GLB GLB SRP SRP GLB GLB GLB GLB V V CCO0 CCO3 V V REF0 REF3 GCLK0 GCLK3 GLB GLB GLB GLB SRP SRP GLB GLB GLB GLB V V CCP0 CCP1 Global Routing Pool PLL0 PLL1 GNDP0 GNDP1 GLB GLB GLB GLB SRP SRP GLB GLB GLB GLB GCLK2 GCLK1 V V REF1 REF2 V V CCO2 CCO1 GLB GLB GLB GLB SRP SRP GLB GLB GLB GLB I/O Bank 1 I/O Bank 2 Overview The ispMACH 5000VG devices consist of multiple SuperWIDE 68-input, 32-macrocell Generic Logic Blocks (GLBs) interconnected by a tiered routing system. Figure 1 shows the functional block diagram of the ispMACH 5000VG. Groups of four GLBs, referred to as segments, are interconnected via a Segment Routing Pool (SRP). Segments are interconnected via the Global Routing Pool (GRP.) Together the GLBs and the routing pools allow designers to create large designs in a single device without compromising performance. Each GLB has 68 inputs coming from the SRP and contains 163 product terms. These product terms form groups of ve product term clusters, which feed the PT sharing array or the macrocell directly. The ispMACH 5000VG allows up to 160 product terms to be connected to a single macrocell via the product term expanders and PT Shar- ing Array. The macrocell is designed to provide exible clocking and control functionality with the capability to select between global, product term and block-level resources. The outputs of the macrocells are fed back into the switch matrices and, if required, the sysIO cell. All I/Os in the ispMACH 5000VG family are sysIOs, which are split into four banks. Each bank has a separate I/O power supply and reference voltage. The sysIO cells allow operation with a wide range of todays emerging inter- face standards. Within a bank, inputs can be set to a variety of standards, providing the reference voltage require- ments of the chosen standards are compatible. Within a bank, the outputs can be set to differing standards, providing the I/O power supply voltage and the reference voltage requirements of the chosen standard are compat- ible. Support for this wide range of standards allows designers to achieve signicantly higher board-level perfor- mance compared to the more traditional LVCMOS standards. 2 TDI RESETB TDO GOE1 TMS GOE2 TCK TOE V CCJ