TM ispXPLD 5000MX Family 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD Family February 2010 Data Sheet Expanded In-System Programmability (ispXP) Features Instant-on capability Flexible Multi-Function Block (MFB) Single chip convenience Architecture In-System Programmable via IEEE 1532 SuperWIDE logic (up to 136 inputs) Interface Arithmetic capability Infinitely reconfigurable via IEEE 1532 or sys- Single- or Dual-port SRAM CONFIG microprocessor interface FIFO Design security Ternary CAM High Speed Operation sysCLOCK PLL Timing Control 4.0ns pin-to-pin delays, 300MHz f MAX Multiply and divide between 1 and 32 Deterministic timing Clock shifting capability Low Power Consumption External feedback capability Typical static power: 20 to 50mA (1.8V), sysIO Interfaces 30 to 60mA (2.5/3.3V) LVCMOS 1.8, 2.5, 3.3V 1.8V core for low dynamic power Programmable impedance Easy System Integration Hot-socketing 3.3V (5000MV), 2.5V (5000MB) and 1.8V Flexible bus-maintenance (Pull-up, pull- (5000MC) power supply operation down, bus-keeper, or none) 5V tolerant I/O for LVCMOS 3.3 and LVTTL Open drain operation interfaces SSTL 2, 3 (I & II) IEEE 1149.1 interface for boundary scan testing HSTL (I, III, IV) sysIO quick configuration PCI 3.3 Density migration GTL+ Multiple density and package options LVDS PQFP and fine pitch BGA packaging LVPECL Lead-free package options LVTTL Table 1. ispXPLD 5000MX Family Selection Guide ispXPLD 5256MX ispXPLD 5512MX ispXPLD 5768MX ispXPLD 51024MX Macrocells 256 512 768 1,024 Multi-Function Blocks 8 16 24 32 Maximum RAM Bits 128K 256K 384K 512K Maximum CAM Bits 48K 96K 144K 192K sysCLOCK PLLs 2 2 2 2 t (Propagation Delay) 4.0ns 4.5ns 5.0ns 5.2ns PD t (Register Set-up Time) 2.2ns 2.8ns 2.8ns 3.0ns S t (Register Clock to Out Time) 2.8ns 3.0ns 3.2ns 3.7ns CO f (Maximum Operating Frequency) 300MHz 275MHz 250MHz 250MHz MAX Functional Gates 75K 150K 225K 300K I/Os 141 149/193/253 193/317 317/381 Packages 208 PQFP 256 fpBGA 256 fpBGA 256 fpBGA 484 fpBGA 484 fpBGA 484 fpBGA 672 fpBGA 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 5kmx 12.4V OSA OSA CC GND PROGRAM TCK TMS TDI OSA OSA TDO V CCJ Lattice Semiconductor ispXPLD 5000MX Family Data Sheet Figure 1. ispXPLD 5000MX Block Diagram ISP Port V V CCO0 CCO3 V V REF0 REF3 MFB MFB sysIO sysIO Bank 0 Bank 3 MFB MFB GCLCK0 GCLCK3 Global V CCP Routing sysCLOCK sysCLOCK PLL 0 PLL 1 Pool GNDP (GRP) GCLK1 GCLK2 sysIO sysIO Bank 1 MFB MFB Bank 2 RESET Optional GOE0 sysCONFIG Interface GOE1 V V REF1 REF2 MFB MFB V V CCO1 CCO2 Introduction The ispXPLD 5000MX family represents a new class of device, referred to as the eXpanded Programmable Logic Devices (XPLDs). These devices extend the capability of Lattices popular SuperWIDE ispMACH 5000 architecture by providing flexible memory capability. The family supports single- or dual-port SRAM, FIFO, and ternary CAM operation. Extra logic has also been included to allow efficient implementation of arithmetic functions. In addition, sysCLOCK PLLs and sysIO interfaces provide support for the system-level needs of designers. The devices provide designers with a convenient one-chip solution that provides logic availability at boot-up, design security, and extreme reconfigurability. The use of advanced process technology provides industry-leading perfor- mance with combinatorial propagation delay as low as 4.0ns, 2.8ns clock-to-out delay, 2.2ns set-up time, and oper- ating frequency up to 300MHz. This performance is coupled with low static and dynamic power consumption. The ispXPLD 5000MX architecture provides predictable deterministic timing. The availability of 3.3, 2.5 and 1.8V versions of these devices along with the flexibility of the sysIO interface helps users meet the challenge of todays mixed voltage designs. Inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. Boundary scan testability further eases inte- gration into todays complex systems. A variety of density and package options increase the likelihood of a good fit for a particular application. Table 1 shows the members of the ispXPLD 5000MX family. Architecture The ispXPLD 5000MX devices consist of Multi-Function Blocks (MFBs) interconnected with a Global Routing Pool. Signals enter and leave the device via one of four sysIO banks. Figure 1 shows the block diagram of the ispXPLD 2