MachXO Family Data Sheet DS1002 Version 03.0, June 2013MachXO Family Data Sheet Introduction June 2013 Data Sheet DS1002 Flexible I/O Buffer Features Programmable sysIO buffer supports wide Non-volatile, Infinitely Reconfigurable range of interfaces: Instant-on powers up in microseconds LVCMOS 3.3/2.5/1.8/1.5/1.2 Single chip, no external configuration memory LVTTL required PCI Excellent design security, no bit stream to LVDS, Bus-LVDS, LVPECL, RSDS intercept sysCLOCK PLLs Reconfigure SRAM based logic in milliseconds Up to two analog PLLs per device SRAM and non-volatile memory programmable Clock multiply, divide, and phase shifting through JTAG port System Level Support Supports background programming of IEEE Standard 1149.1 Boundary Scan non-volatile memory Onboard oscillator Sleep Mode Devices operate with 3.3V, 2.5V, 1.8V or 1.2V Allows up to 100x static current reduction power supply TransFR Reconfiguration (TFR) IEEE 1532 compliant in-system programming In-field logic update while system operates High I/O to Logic Density Introduction 256 to 2280 LUT4s The MachXO is optimized to meet the requirements of 73 to 271 I/Os with extensive package options applications traditionally addressed by CPLDs and low Density migration supported capacity FPGAs: glue logic, bus bridging, bus interfac- Lead free/RoHS compliant packaging ing, power-up control, and control logic. These devices Embedded and Distributed Memory bring together the best features of CPLD and FPGA Up to 27.6 Kbits sysMEM Embedded Block devices on a single chip. RAM Up to 7.7 Kbits distributed RAM Dedicated FIFO control logic Table 1-1. MachXO Family Selection Guide Device LCMXO256LCMXO640LCMXO1200LCMXO2280 LUTs 256 640 1200 2280 Dist. RAM (Kbits) 2.0 6.1 6.4 7.7 EBR SRAM (Kbits) 0 0 9.2 27.6 Number of EBR SRAM Blocks (9 Kbits) 0013 V Voltage 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V CC Number of PLLs 0012 Max. I/O 78 159 211 271 Packages 100-pin TQFP (14x14 mm) 78 74 73 73 144-pin TQFP (20x20 mm) 113 113 113 100-ball csBGA (8x8 mm) 78 74 132-ball csBGA (8x8 mm) 101 101 101 256-ball caBGA (14x14 mm) 159 211 211 256-ball ftBGA (17x17 mm) 159 211 211 324-ball ftBGA (19x19 mm) 271 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1002 Introduction 01.5