LFSC25E-P1-EV Lattice

LatticeSC PCI Express x1 Evaluation Board Users Guide November 2008 Revision: EB24_01.4 LatticeSC PCI Express x1 Lattice Semiconductor Evaluation Board Users Guide Introduction This users guide describes the LatticeSC PCI Express x1 Evaluation Board featuring the LatticeSC LFSCM3GA25 device in a 900 fpBGA package. The stand-alone evaluation PCB provides a functional platform for development and rapid prototyping of applications that require high-speed SERDES interfaces to PCI Express protocols. The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias. The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces. The board has several debugging and analyzing features for complete evaluation of the LatticeSC device. This users guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the Lat- ticeSC FPGA. Figure 1. LatticeSC PCI Express x1 Evaluation Board Features Four SERDES high-speed channels interfaced to SMA test points and clock connections SERDES interface to x1 PCI Express edge ngers RJ-45 interface for Ethernet QDR2 and RLDRAMII memory devices SFP Transceiver cage and associated interface SATA-like connections to SERDES channels Power connections and power sources ispVM programming support On-board and external reference clock sources Interchangeable clock oscillators On-board reference clock management ORCAstra Demonstration Software interface via standard ispVM JTAG connection 2