LFXP10C-L-EV Lattice

LatticeXP Standard Evaluation Board Users Guide June 2008 EB12_02.4 LatticeXP Standard Evaluation Board Lattice Semiconductor Users Guide Introduction The LatticeXP Standard Evaluation Board provides a convenient platform to evaluate, test and debug user designs. The board consists of a LatticeXP-10 FPGA in a 256 fpBGA package, power input jacks, a clock oscillator (33MHz) and I/O connections. The LatticeXP I/Os are connected to a rich variety of interfaces including switches (momen- tary and ON/OFF), LEDs, SMA pads, RJ45, 0.10 headers and PCB test points. The information in this document pertains to boards marked as Rev. A and Rev. B. This marking is located on the front of the board, beneath the Lattice logo. Any information that only applies to either the Rev. A or Rev.B board will be explicitly stated as such. Features Included LatticeXP FPGA: LFXP10C-5F256C or LFXP10E-5F256C On-board power supply (rev. B only) Prototyping area 188 user I/Os, grouped in eight I/O banks Independent voltage control for core, I/O and clock voltages 33MHz on-board oscillator Status LEDs, input switches Lattice ispDOWNLOAD cable AC adapter (rev. B only) Optional Optional SMA connectors (up to 16) for high-speed clock and data interfacing. The board includes pads for these connectors. The SMA connectors must be procured and installed separately by the user. Software Support To target your HDL design to the LatticeXP device, use the ispLEVER design software. You can learn more about ispLEVER on the Lattice web site at: www.latticesemi.com/software. To download your program to the LatticeXP device, use the ispVM System software. ispVM System can be downloaded from the Lattice web site at: www.latticesemi.com/ispvm. ispTRACY in-system logic analysis support (ispTRACY is included with the ispLEVER design software) 2