LIFMD-RPI-EVN Lattice

CrossLink LIF-MD6000 Master Link Board Evaluation Board User Guide EB105 Version 1.0 May 2016 CrossLink LIF-MD6000 Master Link Board Evaluation Board User Guide Contents Acronyms in This Document ................................................................................................................................................. 3 1. Introduction .................................................................................................................................................................. 4 2. Headers and Test Connections ..................................................................................................................................... 6 3. Programming Circuit ..................................................................................................................................................... 7 3.1. Bridging Circuit .................................................................................................................................................... 7 2 3.2. I C Expander ........................................................................................................................................................ 8 4. Power Supply ................................................................................................................................................................ 9 5. Status Indicators ......................................................................................................................................................... 11 References .......................................................................................................................................................................... 12 Technical Support Assistance............................................................................................................................................... 12 Appendix A. LIF-MD6000-ML-EVN-BRD Schematics ........................................................................................................... 13 Appendix B. LIF-MD6000-ML-EVN-BRD Bill of Materials .................................................................................................... 21 Appendix C. SMA-IOL-EVN-BRD Schematics ....................................................................................................................... 27 Appendix D. SMA-IOL-EVN-BRD Bill of Materials................................................................................................................ 28 Appendix E. B-IOL-EVN-BRD Schematics............................................................................................................................. 29 Appendix F. B-IOL-EVN-BRD Bill of Materials ..................................................................................................................... 30 Revision History ................................................................................................................................................................... 31 Figures Figure 1.1. Top View of Master Link Board and its Key Components ................................................................................... 4 Figure 1.2. Bottom View of Master Link Board ..................................................................................................................... 5 Figure 3.1. Programming Block ............................................................................................................................................. 7 Figure 3.2. Bridging Block ..................................................................................................................................................... 8 2 Figure 3.3. I C Expander Block .............................................................................................................................................. 8 Figure 4.1. Power Supply Block ............................................................................................................................................. 9 Tables Table 2.1. Headers and Test Connectors .............................................................................................................................. 6 Table 4.1. Power LEDs ........................................................................................................................................................... 9 Table 4.2. Device Power Rail Summary and Test Points ..................................................................................................... 10 Table 5.1. Status LED I/O Map ............................................................................................................................................ 11 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 EB105-1.0