M5LV-256/68-12YNC Lattice

Select devices have been discontinued. See Ordering Information section for product status. MACH 5 CPLD Family Fifth Generation MACH Architecture FEATURES High logic densities and I/Os for increased logic integration 128 to 512 macrocell densities 68 to 256 I/Os Wide selection of density and I/O combinations to support most application needs 6 macrocell density options 7 I/O options Up to 4 I/O options per macrocell density Up to 5 density & I/O options for each package Performance features to t system needs 5.5 ns t Commercial, 7.5 ns t Industrial PD PD 182 MHz f CNT Four programmable power/speed settings per block Flexible architecture facilitates logic design Multiple levels of switch matrices allow for performance-based routing 100% routability and pin-out retention Synchronous and asynchronous clocking, including dual-edge clocking Asynchronous product- or sum-term set or reset 16 to 64 output enables Functions of up to 32 product terms Advanced capabilities for easy system integration 3.3-V & 5-V JEDEC-compliant operations IEEE 1149.1 compliant for boundary scan testing 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port PCI compliant (-5/-6/-7/-10/-12 speed grades) Safe for mixed supply voltage system design Bus-Friendly Inputs & I/Os Individual output slew rate control Hot socketing Programmable security bit 2 Advanced E CMOS process provides high performance, cost effective solutions Publication 20446 Rev: J Amendment/0 Issue Date: April 2002Select devices have been discontinued. See Ordering Information section for product status. 1 Table 1. MACH 5 Device Features M5-128/1 M5-192/1 M5-256/1 M5-320 M5-384 M5-512 Feature M5LV-128 M5LV-256 M5LV-320 M5LV-384 M5LV-512 Supply Voltage (V) 5 3.3 5 5 3.3 5 3.3 5 3.3 5 3.3 Macrocells 128 128 192 256 256 320 320 384 384 512 512 Maximum User I/O Pins 120 120 120 160 160 192 160 160 160 256 256 t (ns) 5.5 5.5 5.5 5.5 5.5 6.5 6.5 6.5 6.5 6.5 6.5 PD t (ns) 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 SS t (ns) 4.5 4.5 4.5 4.5 4.5 5.0 5.0 5.0 5.0 5.0 5.0 COS f (MHz) 182 182 182 182 182 167 167 167 167 167 167 CNT Typical Static Power (mA) 35 35 45 55 55 70 70 75 75 100 100 IEEE 1149.1 Boundary Scan Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PCI-Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Note: 1. M5-xxx is for 5-V devices. M5LV-xxx is for 3.3-V devices. GENERAL DESCRIPTION The MACH 5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low power, and supports additional features such as in-system programmability, Boundary Scan testability, and advanced clocking options (Table 1). The MACH 5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation. 2 Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E CMOS process technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The 5.5, 6.5, 7.5, 10, and 12- ns devices are compliant with the PCI Local Bus Specification. 2 MACH 5 Family