ispClock5312S Evaluation Board
Users Guide
August 2007
Revision: EB32_01.0
ispClock5312S Evaluation Board
Lattice Semiconductor Users Guide
Introduction
The family of ispClock5300S devices from Lattice Semiconductor Corporation provide in-system-programmable
zero delay universal fan-out buffers for use in clock distribution applications. Single-ended ultra low skew outputs
are organized with two outputs per bank. Each pair of outputs may be independently congured to support sepa-
rate I/O standards (LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output
provides independent programmable control of termination, slew-rate, and timing skew. All conguration informa-
2
tion is stored on chip in non-volatile E CMOS memory.
The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the
on-chip low jitter high-performance phase locked loop (PLL). A set of three programmable 5-bit counters can be
used to generate three frequencies derived from the PLL clock. These counters are programmable in powers of 2
only (1, 2, 4, 8, 16, 32). The clock output from any of the V-dividers can then be routed to any clock output pair
through the output routing matrix. The output routing matrix also enables routing of reference clock inputs directly
to any output. For additional details, please refer to the ispPAC-CLK5300S Family Data Sheet.
Figure 1. ispClock5312S Evaluation Board
2