LS7210 LSI LS7210 LSI/CSI U L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 June 2006 PROGRAMMABLE DIGITAL DELAY TIMER PIN ASSIGNMENT - TOP VIEW FEATURES: Programmable Delay from 6ms toInfinit 1 14 VSS (+V) B Can be Cascaded for Sequential Events or Extended Delay +4.75V to +15V Operation (Vss - VDD) 2 13 A OUT On Chip Oscillator or External Clock time base High Noise Immunity 3 12 WB0 TRIGGER LS7210 (DIP) LS7210-S (SOIC) - (See Figure 1) 4 11 WB1 CLOCK SELECT DESCRIPTION: 5 10 WB2 OSCILLATOR The LS7210 is a MOS programmable digital timer that can generate a delay in the range of 6ms to infinity. The delay is programmed by 5 9 WB3 EXTERNAL CLOCK 6 binary weighted input bits in combination with the time base pro- vided. The chip can be operated in four different modes: Delayed 7 8 V DD (-V) WB4 Operate, Delayed Release, Dual Delay and One Shot. These modes are selected by the control inputs A and B. FIGURE 1 INPUT/OUTPUT DESCRIPTION: TABLE 1. WEIGHTING BITS ASSIGNMENTS OSCILLATOR Input (Pin 5) The frequency of the internal oscillator is set by an RC network con- INPUTS VALUE nected to the OSC input, as shown in Figure 2. The nominal os- WB0 1 cillator frequency, f, at room temperature is given by f 1/RC where WB1 2 R values range from a minimum of 47K to a maximum 3M. WB2 4 NOTE: Oscillation accuracy from chip to chip for a fixed value of RC, WB3 8 is + 10%. (Parts can supplied to tighter tolerances.) WB4 16 EXTERNAL CLOCK Input (Pin 6) Example: For a weighting factor of 25, inputs WB4, WB3, and If the internal oscillator is not used, the chip can be driven by an ex- WB0 should be programmed to logic 0. ternal clock applied to this input. MODE SELECT Inputs A, B (Pins 2, 1) CLOCK SELECT Input (Pin 4) The chip can be programmed to operate in four different modes The internal oscillator or the external clock is selected by the proper by applying the logic levels to inputs A and B as indicated in logic level applied to this input. A logic 1 selects the external clock Table 2. The mode select inputs are clocked into the input latch- and logic 0 selects the internal oscillator. (See Note 1) es with the negative edge of the time base clock. These inputs should not be changed while a delay timing is in progress. TRIGGER Input (Pin 3) (See Note 1) A positive or a negative transition at the trigger input initiates a delay TABLE 2. MODE SELECTION in turning on or off the output. A negative transition always turns on the output with or without delay depending on the selected mode. A CONTROL MODE positive transition at the trigger input always turns off the output (with A B the exception of one-shot mode) with or without delay depending on 1 1 Dual Delay the selected mode. The delay is a function of the time base fre- 1 0 Delayed Release quency and the weighting factor programmed at the weighting bit in- 0 1 Delayed Operate puts. The trigger input is clocked into the input latch with the neg- 0 0 One Shot ative edge of the selected time base clock. All timings begin after the latch has been set up. (See Note 1) OUT Output (Pin 13) The output is an open drain FET. To obtain proper switching of the output between Logic 0 and 1 levels, an external pull down re- WEIGHTING FACTOR Inputs, WB0-WB4 (Pins 12-8) sistor to VDD must be used. If the output is used only as a current A delay from the trigger input to the output is programmed by ap- source, no such pull down is needed. The output is logically in- plying 1 s complement binary weighted numbers at these 5 inputs. verted with respect to the trigger input. (See Note 1) The exact equation for the delay is: VSS, VDD (Pins 14, 9) (1 + 1, 023N) f = Oscillation Frequency Supply voltage positive, negative terminals. Delay = f N = Weighting Factor NOTE 1: These inputs have internal pullup resistors. 7210-061606-1DELAYED RELEASE MODE MODE DEFINITION TIMING DIAGRAM: (See Figure 3) This mode causes a retriggerable delay in turning off the output whenever there is a positive transition at the trigger input. The out- DUAL DELAY MODE put is turned on without delay in response to a negative transition at Thls is the Default Mode when the inputs A and B are left un- the trigger input. programmed. The function of the Dual Delay mode is to provide a time delay on both the turn-on and turn-off of the output. Once turned ONE-SHOT MODE on, the output will remain on as long as the trigger input is Logic 0. In this mode, the chip functions like a retriggerable monostable Once turned off, the output will remain off as long as the trigger input multi-vibrator. The output is turned on whenever there is a negative is a logic 1. transition at the trigger input. At the end of the programmed delay, the output is turned off automatically. If there is a negative transition DELAYED OPERATE MODE at the trigger input before the delay is over, the delay is restarted. This mode causes a retriggerable delay in turning the output on in re- A positive transition at the trigger input has no effect on the output sponse to a negative edge at the trigger input. The output is turned in this mode. NOTE: In One-Shot mode, the TRIGGER input must off without delay in response to a positive transition at the trigger in- be held at logic 1 during a power-up. put. ABSOLUTE MAXIMUM RATINGS: (All voltages referenced to VDD) SYMBOL VALUE UNIT DC Supply Voltage VSS +18 V Voltage (Any Pin) VIN 0 to VSS + 0.3 V Operating Temperature TA -25 to +70 C Storage Temperature TSTG -65 to +150 C DC ELECTRICAL CHARACERISTICS: (-25C TA +70C unless otherwise specified. All voltages referenced to VDD) PARAMETER SYMBOL MIN MAX UNIT CONDITION Suppy Voltage VSS +4.75 +15.0 V Supply Current ISS - 3.0 mA VSS = +15V, output off Trigger Input Logic 1 VTH VSS - 1 VSS V - Logic 0 VTL 0 0.2VSS V - All Other Inputs Logic 1 VIH 0.8VSS VSS V - Logic 0 VIL 0 0.2VSS V - Output Source Current Io +1.0 - mA VSS = + 5V for Vo = Vss - 1V Io +2.8 - mA VSS = +10V Io +4.2 - mA VSS = +15V SWITCHING CHARACTERISTICS: (See Figure 4) PARAMETER SYMBOL MIN MAX UNIT Oscillator Frequency fOSC - 50 kHz External Clock Frequency fext DC 160 kHz External Clock, Positive Pulse Width tH 3 - s External Clock, Negative Pulse Width tL 3 - s A, B and Trigger Input Set-Up Time tS - 300 ns Time-base Clock to Output Delay (turn-on delay in Delayed Release mode and turn-off delay in Delayed Operate mode) tnd - 1 s Time-base Clock to Output Delay at the End of Time Out tod - 1.6 s Time-base Clock to Output Delay tsd - 600 ns (turn-on delay in One- Shot Mode) 7210-061606-2