CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1B Data Sheet CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters (ADCs) FEATURES General Description n 10-bit resolution The CDK1308 is a high performance ultra low power analog-to-digital n 20/40/65/80MSPS max sampling rate converter (ADC). The ADC employs internal reference circuitry, a CMOS n Ultra-Low Power Dissipation: control interface and CMOS output data, and is based on a proprietary 15/25/38/46mW structure. Digital error correction is employed to ensure no missing codes in n 61.6dB SNR at 80MSPS and 8MHz F IN the complete full scale range. n Internal reference circuitry Two idle modes with fast startup times exist. The entire chip can either be n 1.8V core supply voltage put in Standby Mode or Power Down mode. The two modes are optimized to n 1.7 3.6V I/O supply voltage allow the user to select the mode resulting in the smallest possible energy n Parallel CMOS output consumption during idle mode and startup. n 40-pin QFN package n Pin compatible with CDK1307 The CDK1308 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and APPLICATIONS supports LVDS, LVPECL, sine wave, and CMOS clock inputs. n Medical Imaging n Portable Test Equipment Functional Block Diagram n Digital Oscilloscopes n IF Communication n Video Conferencing n Video Distribution 10 Ordering Information Part Number Speed Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CDK1308AILP40 20MSPS QFN-40 Yes Yes -40C to +85C Tray CDK1308BILP40 40MSPS QFN-40 Yes Yes -40C to +85C Tray CDK1308CILP40 65MSPS QFN-40 Yes Yes -40C to +85C Tray CDK1308DILP40 80MSPS QFN-40 Yes Yes -40C to +85C Tray Moisture sensitivity level for all parts is MSL-2A. Exar Corporation www.exar.com 48720 Kato Road, Fremont CA 94538, USA Tel. +1 510 668-7000 - Fax. +1 510 668-7001CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1B Data Sheet Pin Configuration QFN-40 DVDD D 4 1 30 CM EXT 2 29 D 3 AVDD D 2 3 28 AVDD 4 27 CLK EXT CDK1308 IP OVDD 5 QFN-40 26 IN 6 25 OVDD AVDD ORNG 7 24 DVDDCLK 8 23 D 1 CLKP D 0 9 22 CLKN 10 21 NC Pin Assignments Pin No. Pin Name Description 0 Ground connection for all power domains. Exposed pad VSS 1, 11, 16 DVDD Digital and I/O-ring pre driver supply voltage, 1.8V 2 Common Mode voltage output CM EXT 3, 4, 7 Analog supply voltage, 1.8V AVDD 5, 6 IP, IN Analog input (non-inverting, inverting) 8 DVDDCLK Clock circuitry supply voltage, 1.8V 9 Clock input, non-inverting (format: LVDS, LVPECL, CMOS/TTL, Sine Wave) CLKP 10 Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground CLKN 12 CLK EXT EN CLK EXT signal enabled when low (zero). Tristate when high. 13 DFRMT Data format selection. 0: Offset Binary, 1: Two s Complement 14 Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up PD N always apply Power Down mode before using Active Mode to reset chip. 15 OE N Output Enable. Tristate when high 17, 18, 25, I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V OVDD 26, 36, 37 19 NC 20 NC 21 NC 22 Output Data (LSB) D 0 2009-2013 Exar Corporation 2/14 Rev 1B DVDD 11 40 SLP N CLK EXT EN 12 39 CM EXTBC 0 DFRMT CM EXTBC 1 13 38 PD N 14 37 OVDD OE N OVDD 15 36 DVDD D 9 16 35 OVDD 17 34 D 8 OVDD D 7 18 33 NC D 6 19 32 NC 20 31 D 5