CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters Rev 2C Data Sheet CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters FEATURES General Description n 13-bit resolution The CDK2307 is a high performance, low power dual Analog-to-Digital Con- n 20/40/65/80MSPS maximum sampling rate verter (ADC). The ADC employs internal reference circuitry, a CMOS control n Ultra-low power dissipation: 30/55/85/102mW interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the com- n SNR 72dB at 80MSPS and 8MHz F IN plete full scale range. n Internal reference circuitry n Several idle modes with fast startup times exist. Each channel can be inde- 1.8V core supply voltage pendently powered down and the entire chip can either be put in Standby n 1.7V 3.6V I/O supply voltage Mode or Power Down mode. The different modes are optimized to allow the n Parallel CMOS output user to select the mode resulting in the smallest possible energy consumption n 64-pin QFN package during idle mode and startup. n Dual channel The CDK2307 has a highly linear THA optimized for frequencies up to 70MHz. n Pin compatible with CDK2308 The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave and CMOS clock inputs. APPLICATIONS n Handheld Communication, PMR, SDR Functional Block Diagram n Medical Imaging n Portable Test Equipment n Digital Oscilloscopes n Baseband / IF Communication n Video Digitizing CLK EXT n CCD Digitizing Ordering Information Part Number Speed Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CDK2307AILP64 20MSPS QFN-64 Yes Yes -40C to +85C Tray CDK2307BILP64 40MSPS QFN-64 Yes Yes -40C to +85C Tray CDK2307CILP64 65MSPS QFN-64 Yes Yes -40C to +85C Tray CDK2307DILP64 80MSPS QFN-64 Yes Yes -40C to +85C Tray Moisture sensitivity level for all parts is MSL-2A. Exar Corporation www.exar.com 48720 Kato Road, Fremont CA 94538, USA Tel. +1 510 668-7000 - Fax. +1 510 668-7001 CLKP CLKNCDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters Rev 2C Data Sheet Pin Configuration QFN-64 1 48 2 47 3 46 4 45 5 44 6 43 CDK2307 7 42 CLK EXT QFN-64 8 41 9 40 10 39 11 38 12 37 DVSSCLK 13 36 DVDDCLK 14 35 CLKP 15 34 CLKN 16 33 Pin Assignments Pin No. Pin Name Description 1, 18, 23 DVDD Digital and I/O-ring pre driver supply voltage, 1.8V 2 CM EXT Common Mode voltage output 3, 9, 12 AVDD Analog supply voltage, 1.8V 4, 5, 8 AVSS Analog ground 6, 7 IP0, IN0 Analog input Channel 0 (non-inverting, inverting) 10, 11 IP1, IN1 Analog input Channel 1 (non-inverting, inverting) 13 DVSSCLK Clock circuitry ground 14 DVDDCLK Clock circuitry supply voltage, 1.8V 15 CLKP Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave) 16 CLKN Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground 17, 64 DVSS Digital circuitry ground 19 CLK EXT EN CLK EXT signal enabled when low (zero). Tristate when high. 20 DFRMT Data format selection. 0: Offset Binary, 1: Two s Complement 21 PD N Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up, always apply Power Down mode before using Active Mode to reset chip. 22 OE N 1 Output Enable Channel 0. Tristate when high. 24, 41, 58 OVDD I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V. 25, 40, 57 OVSS Ground for I/O ring 26 D1 0 Output Data Channel 1 (LSB, 13-bit output or 1V full scale range ) pp 27 D1 1 Output Data Channel 1 (LSB, 12-bit output 2V full scale range) pp 28 D1 2 Output Data Channel 1 29 D1 3 Output Data Channel 1 2009-2013 Exar Corporation 2/16 Rev 2C 17 64 18 63 CLK EXT EN 19 62 20 61 21 60 22 59 23 58 24 57 56 25 55 26 54 27 53 28 29 52 30 51 31 50 32 49