XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO APRIL 2013 REV. 3.1.0 FEATURES GENERAL DESCRIPTION Added feature in devices with top mark date code of 1 The XR16C854/854D (854) is an enhanced quad F2 YYW and newer: Universal Asynchronous Receiver and Transmitter 5 volt tolerant inputs (UART) each with 128 bytes of transmit and receive 2.97 to 5.5 Volt Operation FIFOs, transmit and receive FIFO counters and trigger levels, automatic hardware and software flow Pin-to-pin compatible with the industry standard control, and data rates of up to 2 Mbps. ST16C554 and ST16C654 and TIs TL16C554N and TL16C754BFN Each UART has a set of registers that provide the Intel or Motorola Data Bus Interface select user with operating status and control, receiver error indications, and modem serial interface controls. Four independent UART channels System interrupts may be tailored to meet design Register Set Compatible to 16C550 requirements. An internal loopback capability allows Data rates of up to 2 Mbps onboard diagnostics. Transmit and Receive FIFOs of 128 bytes The 854 is available in 64-pin LQFP, 68-pin PLCC Programmable TX and RX FIFO Trigger Levels and 100-pin QFP packages. The 64-pin package Transmit and Receive FIFO Level Counters only offers the 16 mode interface, but the 68 and 100 Automatic Hardware (RTS/CTS) Flow Control pin packages offer an additional 68 mode interface Selectable Auto RTS Flow Control Hysteresis which allows easy integration with Motorola Automatic Software (Xon/Xoff) Flow Control processors. Wireless Infrared (IrDA 1.0) Encoder/Decoder The XR16C854CV (64 pin) offers three state interrupt Sleep Mode (200 uA typical) outputs while the XR16C854DV provides continuous interrupt outputs. The 100 pin package provides Crystal oscillator or external clock input additional FIFO status outputs (TXRDY and APPLICATIONS RXRDY A-D), separate infrared transmit data outputs (IRTX A-D) and channel C external clock Portable Appliances input (CHCCLK). The XR16C854/854D is compatible Telecommunication Network Routers with the industry standard ST16C554/554D and Ethernet Network Routers ST16C654/654D. Cellular Data Devices NOTE: 1 Covered by U.S. Patent 5,649,122 and 5,949,787. Factory Automation and Process Control FIGURE 1. XR16C854 BLOCK DIAGRAM 2.97V to 5.5V VCC A2:A0 GND D7:D0 UART Channel A IOR 128 Byte TX FIFO UART TXA, RXA, IRTXA, DTRA , IOW Regs IR DSRA , RTSA , CTSA , TX & RX CSA ENDEC CDA , RIA , OP2A BRG CSB 128 Byte RX FIFO CSC TXB, RXB, IRTXB, DTRB , CSD UART Channel B DSRB , RTSB , CTSB , (same as Channel A) INTA Data Bus CDB , RIB , OP2B INTB Interface INTC TXC, RXC, IRTXC, DTRC , UART Channel C INTD DSRC , RTSC , CTSC , (same as Channel A) CDC , RIC , OP2C CHCCLK TXRDY A-D TXD, RXD, IRTXD, DTRD , UART Channel D RXRDY A-D DSRD , RTSD , CTSD , (same as Channel A) Reset CDD , RID , OP2D 16/68 XTAL1 INTSEL Crystal Osc/Buffer XTAL2 854 BLK Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com TXRDYD 81 50 RXRDYC RXRDYD 82 49 CDC CDD 83 48 RIC RID 84 47 RXC RXD 85 46 GND VCC 86 45 TXRDY GND 87 44 RXRDY D0 88 43 RESET D1 89 42 CHCCLK D2 90 41 XTAL2 D3 91 40 XTAL1 D4 92 A0 39 D5 93 8 A1 3 D6 94 37 A2 D7 95 36 16/68 GND 96 CLKSEL 35 RXA 97 RXB 34 RIA 98 33 RIB CDA 99 32 CDB RXRDYA 100 31 RXRDYB XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO REV. 3.1.0 FIGURE 2. PIN OUT ASSIGNMENT FOR 100-PIN QFP PACKAGES IN 16 AND 68 MODE TXRDYD 81 50 RXRDYC RXRDYD 82 49 CDC CDD 83 48 RIC 84 RID 47 RXC RXD 85 46 GND VCC 86 45 TXRDY INTSEL 87 44 RXRDY XR16C854 RESET D0 88 43 100-pin QFP D1 89 42 CHCCLK 16 Mode D2 90 XTAL2 41 Connect 16/68 pin to VCC D3 91 40 XTAL1 D4 92 39 A0 D5 93 38 A1 D6 94 37 A2 D7 95 36 16/68 GND 96 35 CLKSEL RXA 97 34 RXB RIA 98 33 RIB CDA 99 CDB 32 RXRDYA 100 31 RXRDYB XR16C854 100-pin QFP 68 Mode Connect 16/68 pin to GND 2 N.C. 1 80 N.C. N.C. 2 79 N.C. N.C. 3 78 N.C. N.C. 4 77 N.C. TXRDYA 5 76 FSRS 6 IRTXA 75 IRTXD DSRA 7 74 DSRD CTSA 8 73 CTSD DTRA 9 72 DTRD 10 VCC 71 GND RTSA 11 70 RTSD IRQ 12 69 N.C. CS 13 68 N.C. 14 TXA 67 TXD R/W 15 66 N.C. TXB 16 TXC 65 A3 17 64 A4 18 N.C. 63 N.C. RTSB 19 62 RTSC GND 20 61 VCC DTRB 21 60 DTRC CTSB 22 59 CTSC DSRB 23 58 DSRC IRTXB 24 IRTXC 57 TXRDYB 25 56 TXRDYC N.C. 26 55 N.C. N.C. 27 54 N.C. N.C. 28 53 N.C. 29 N.C. 52 N.C. N.C. 30 51 N.C. 1 N.C. 80 N.C. N.C. 2 79 N.C. N.C. 3 78 N.C. N.C. 4 77 N.C. TXRDYA 5 FSRS 76 IRTXA 6 75 IRTXD DSRA 7 74 DSRD CTSA 8 73 CTSD DTRA 9 72 DTRD VCC 10 71 GND RTSA 11 70 RTSD INTA 12 69 INTD CSA 13 68 CSD TXA 14 67 TXD 15 IOW 66 IOR TXB 16 65 TXC 17 CSB 64 CSC 18 INTB 63 INTC RTSB 19 62 RTSC GND 20 61 VCC DTRB 21 DTRC 60 CTSB 22 59 CTSC DSRB 23 58 DSRC 24 IRTXB 57 IRTXC 25 TXRDYB 56 TXRDYC N.C. 26 55 N.C. N.C. 27 54 N.C. N.C. 28 N.C. 53 N.C. 29 52 N.C. N.C. 30 51 N.C.