XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO DECEMBER 2009 REV. 1.0.1 FEATURES GENERAL DESCRIPTION Pin-to-pin compatible with XR16L570 in 24-QFN 1 The XR16M570 (M570) is an enhanced Universal and 32-QFN packages Asynchronous Receiver and Transmitter (UART) with 16 bytes of transmit and receive FIFOs, selectable Intel data bus Interface transmit and receive FIFO trigger levels, automatic 16 Mbps maximum data rate hardware and software flow control, and data rates of up to 16 Mbps at 3.3V, 12.5 Mbps at 2.5V and 7.5 Selectable TX/RX FIFO Trigger Levels Mbps at 1.8V with 4X data sampling rate. TX/RX FIFO Level Counters The Auto RS-485 Half-Duplex Direction control Independent TX/RX Baud Rate Generator feature simplifies both the hardware and software for half-duplex RS-485 applications. In addition, the Fractional Baud Rate Generator Multidrop mode with Auto Address detection Auto RTS/CTS Hardware Flow Control increases the performance by simplifying the software routines. Auto XON/XOFF Software Flow Control The Independent TX/RX Baud Rate Generator Auto RS-485 Half-Duplex Direction Control feature allows the transmitter and receiver to operate Multidrop mode w/ Auto Address Detect at different baud rates. Power consumption of the M570 can be minimized by enabling the sleep mode Sleep Mode with Automatic Wake-up and PowerSave mode. PowerSave mode in 24-pin QFN package The M570 has a 16550 compatible register set that Infrared (IrDA 1.0 and 1.1) mode provide users with operating status and control, receiver error indications, and modem serial interface 1.62V to 3.63V supply operation controls. An internal loopback capability allows Crystal oscillator or external clock input onboard diagnostics. The M570 is available in 24-pin QFN, 32-pin QFN and 25-pin BGA packages. All APPLICATIONS three packages offer the 16 mode (Intel bus) interface Personal Digital Assistants (PDA) only. Cellular Phones/Data Devices NOTE: 1 Covered by U.S. Patent 5,649,122. Battery-Operated Devices Global Positioning System (GPS) Bluetooth FIGURE 1. XR16M570 BLOCK DIAGRAM VCC PwrSave (1.62 to 3.63 V) A2:A0 GND D7:D0 UART IOR TX, RX, IOW 16 Byte TX FIFO UART RTS , CTS , CS Regs DTR , DSR , TX & IR RI , CD ENDEC RX INT Intel BRG 16 Byte RX FIFO RESET Data Bus Interface XTAL1 Crystal Osc/Buffer XTAL2 Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.1 FIGURE 2. PIN OUT ASSIGNMENT FOR 24-PIN QFN, 32-PIN QFN AND 25-BGA PACKAGES 24 23 22 21 20 19 18 17 18 17 16 15 14 13 DSR 25 16 NC VCC 19 12 A2 CD 26 15 NC D0 20 11 IOR RI 14 IOR 27 D1 21 10 GND VCC 32-pin QFN 28 13 GND 24-pin QFN 29 D2 22 9 IOW D0 12 IOW 30 D1 XTAL 2 11 23 8 D3 CLK 31 D2 10 XTAL 1 24 7 D4 PwrSave 32 D3 9 NC 1 234 56 234 5 6 78 1 A1 Corner 1 2 3 4 5 A B C D E Transparent Top View CTS RESET INT A1 A2 VCC DTR RTS A0 IOR D0 D6 D7 DSR IOW D3 D1 TX CS XTAL1 D4 D2 D5 RX GND ORDERING INFORMATION OPERATING TEMPERATURE PART NUMBER PACKAGE DEVICE STATUS RANGE XR16M570IL24 24-Pin QFN -40C to +85C Active XR16M570IL32 32-Pin QFN -40C to +85C Active XR16M570IB25 25-Pin BGA -40C to +85C Active 2 CTS D5 Reset D6 RTS D7 INT RX A0 TX A1 CS D4 CTS NC RESET D5 DTR D6 RTS INT D7 RX A0 TX A1 CS A2