XR20M1170IG24-F MaxLinear

XR20M1170 I2C/SPI UART WITH 64-BYTE FIFO JUNE 2019 REV. 1.1.2 FEATURES GENERAL DESCRIPTION 1.62 to 3.6 Volt operation 1 The XR20M1170 is a high performance universal 2 asynchronous receiver and transmitter (UART) with Selectable I C/SPI interface 2 64 byte TX and RX FIFOs and a selectable I C/SPI SPI clock frequency up to slave interface. The XR20M1170 operates from 1.62 18MHz at 3.3V to 3.63 volts. The enhanced features in the XR20M1170 include a programmable fractional baud 16MHz at 2.5V rate generator, an 8X and 4X sampling rate that 8MHz at 1.8V allows for a maximum baud rate of 16Mbps at 3.3V. Full-featured UART The standard features include 16 selectable TX and RX FIFO trigger levels, automatic hardware (RTS/ Data rate of up to 16Mbps at 3.3V CTS) and software (Xon/Xoff) flow control, and a Data rate of up to 12.5Mbps at 2.5V complete modem interface. Onboard registers Data rate of up to 8Mbps at 1.8V provide the user with operational status and data Fractional baud rate generator error flags. An internal loopback capability allows system diagnostics. The XR20M1170 is available in Transmit and receive FIFOs of 64 bytes the 24-pin QFN, 16-pin QFN, 24-pin TSSOP and 16- 16 selectable TX and RX FIFO trigger levels pin TSSOP packages. Automatic hardware (RTS/CTS) flow control NOTE: 1 Covered by U.S. Patent 5,649,122 Automatic software (Xon/Xoff) flow control APPLICATIONS Halt and resume transmission control Automatic RS-485 half-duplex direction control Portable appliances output via RTS Battery-operated devices Wireless Infrared (IrDA 1.0 and 1.1) encoder/ Cellular data devices decoder Automatic sleep mode (< 15uA at 3.3V) Factory automation and process controls General purpose I/Os Full modem interface Crystal oscillator (up to 24MHz) or external clock (up to 64MHz) input 24-QFN, 16-QFN, 24-TSSOP, 16-TSSOP packages FIGURE 1. XR20M1170 BLOCK DIAGRAM VCC 1.62V 3.63V 64 Byte TX TX FIFO 64 Byte IRQ RX RX FIFO UART Regs RTS CTS SDA GPIOs 2 SCL GPIO 7:0 I C/SPI A0/CS Interface BRG A1/SI SO XTAL1 Crystal Osc/Buffer XTAL2 I2C/SPI 1XR20M1170 I2C/SPI UART WITH 64-BYTE FIFO REV. 1.1.2 FIGURE 2. PIN OUT ASSIGNMENT VCC 1 24 GPIO7/RI GPIO6/CD A0/CS 2 23 A1/SI 3 22 CTS 18 17 16 15 14 13 SO 4 21 RESET CTS SDA 19 12 GPIO0 5 20 GPIO4/DSR GPIO6/CD 20 11 GND 24-Pin 6 GPIO5/DTR GPIO1 19 GPIO7/RI 21 10 GPIO3 TSSOP 24-Pin QFN I2C/SPI 7 18 RTS VCC 22 9XTAL2 RX 8 17 IRQ A0/CS 23 8 XTAL1 A1/SI 24 7 GPIO2 TX 16 SCL 9 1 23456 GPIO2 10 15 SDA XTAL1 11 14 GND XTAL2 12 13 GPIO3 A0/CS 1 16 VCC A1/SI 2 15 CTS 12 11 10 9 SO 3 14 RESET CTS 13 8 SDA I2C/SPI 4 13 RTS 16-Pin 16-Pin 14 7 VCC GND TSSOP QFN 5 12 IRQ RX A0/CS 15 6 XTAL2 6 SCL TX 11 16 5 A1/SI XTAL1 XTAL1 7 10 SDA 1234 XTAL2 8 9 GND 2 RESET SO GPIO4/DSR RESET SO GPIO0 RTS I2C/SPI GPIO5/DTR GPIO1 IRQ RX RTS I2C/SPI SCL TX IRQ RX SCL TX