XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO MARCH 2018 REV. 1.0.2 FEATURES GENERAL DESCRIPTION 128 Byte Transmit and Receive FIFO The XR28V382 (V382) is a dual Universal Asynchronous Receiver and Transmitter (UART) for Compliant to LPC 1.1 Specifications the Intel Low Pin Count (LPC) bus interface. This -40C to +85C Industrial Temp Operation device can replace or supplement a Super I/O device to add additional serial ports to the system. Watchdog Timer with WDTOUT signal The V382 UARTs support any 16-bit I/O address 2 independent UART channels supported by the system. The register set is based on Programmable I/O mapped base addresses the industry standard 16550 UART, so the V382 Data rates up to 3 Mbps operates with standard serial port drivers without requiring a custom driver to be installed. Selectable RX FIFO interrupt trigger levels Auto RS-485 Half-Duplex Control mode The 128 byte Transmit and Receive FIFOs reduce CPU overhead and minimize the chance of buffer Programmable character lengths (5, 6, 7, 8) overflow and data loss. In addition to the 16550 UART with even, odd, or no parity registers, there are also Configuration register set IrDA mode and separate IRTXA and IRRXA where enhanced features such as the 9-bit (multidrop) pins for the first UART channel mode, IrDA mode and the Watchdog Timer can be 9-bit (Multidrop) mode enabled. External 24MHz/48MHz clock The V382 is available in a 32-pin QFN package. Single 3.3V Supply Voltage ( 10%) APPLICATIONS 5V tolerant inputs Industrial and Embedded PCs 32-QFN package (5mm x 5mm) Factory Automation and Process Controls Network Routers System Board Designs FIGURE 1. XR28V382 BLOCK DIAGRAM VCC 3.3V 10% GND TXA / PS 3F8 IRQA TX FIFO Baud (IrDA Encoder) IRTXA / PS CONF KEY0 Rate Generator PCIRST RXA LCLK LPC RX FIFO (IrDA Decoder) LFRAME Bus IRRXA LAD 3:0 Interface SERIRQ Status and RTSA /PS CONF 2E/RS485 Control Modem IOs DTRA /PS 3E0 IRQA Registers CTSA , DSRA , CDA , RIA Global UART Channel A Configuration Registers Baud TX FIFO TXB / PS 2F8 IRQB Watch Rate WDTOUT / Dog Generator PS WDT Timer RX FIFO RXB Status and RTSB /PS CONF KEY1/RS485 Clock Control CLKIN Modem IOs Divider DTRB /PS 2E0 IRQB Registers CTSB , DSRB , CDB , RIB UART Channel B 1XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 FIGURE 2. PIN OUT ASSIGNMENT 31 30 29 28 27 26 25 32 1 24 RXB GND 2 23 LAD3 DTRB /PS 2E0 IRQB XR28V382 3 22 LAD2 RTSB /PS CONF KEY1/RS485 32-pin QFN 4 21 LAD1 VCC 5 20 GND LAD0 6 19 WDTOUT /PS WDT LCLK 7 18 CDA LFRAME E PAD VCC 8 17 RIA 10 11 12 13 14 15 16 9 (1) Ordering Information PART NUMBER OPERATING TEMPERATURE RANGE LEAD-FREE PACKAGE PACKAGING METHOD XR28V382IL32-F Tray (2) -40C to +85C 32-Lead QFN Yes XR28V382IL32TR-F Tape and Reel XR28V382IL32-0A-EB XR28V382 Evaluation Board NOTES: 1. Refer to www.exar.com/XR28V382 for most up-to-date Ordering Information. 2. Visit www.exar.com for additional information on Environmental Rating. 2 CLKIN PCIRST IRTXA /PS CONF KEY0 CTSB IRRXA DSRB SERIRQ TXA/PS 3F8 IRQA RXA CDB RIB DTRA /PS 3E0 IRQA RTSA /PS CONF 2E/RS485 CTSA DSRA TXB/PS 2F8 IRQB