XRD9814B/XRD9816B 3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors November 2002-2 FEATURES 14-Bit or 8-Bit (Nibble) Parallel Data Output 14-Bit (XRD9814B) or 16-Bit (XRD9816B) A/D Converter (XRD9814B) 16-Bit or 8-Bit (Nibble) Parallel Data Output Triple-Channel, 2.5 MSPS Color Scan Mode Single-Channel, 6 MSPS Monochrome Scan (XRD9816B) Mode 5V Operation and 3V I/O Compatibility Low Power CMOS: 500mW 5V Triple Correlated Double Sampler Triple 10-Bit Programmable Gain Amplifier APPLICATIONS Triple 10-Bit Offset Compensation DAC Fully Differential or Single-Ended Inputs 48-Bit Color Scanners (XRD9816B) CDS or S/H Mode 42-Bit Color Scanners (XRD9814B) Inverting or Non-Inverting Mode CCD or CIS Color Imagers Internal Voltage Reference Gray Scale Scanners Serial Control: On Data Bus or Separate Pins Film Scanners Improved PGA Performance GENERAL DESCRIPTION The CDS mode of operation supports both line and The XRD9814B/9816B is a fully integrated, high-per- formance analog signal processor/digitizer specifi- pixel-clamp modes and can be used to achieve signifi- cant reduction in system 1/f noise and CCD reset cally designed for use in 3-channel linear Charge Coupled Device (CCD) and Contact Image Sensitive clock feed-through. In S/H mode the internal DC- (CIS) imaging applications. restore voltage clamp can be enabled or disabled to support AC-coupled or DC inputs. Sampling mode, 10-bit PGA gain (1024 linear steps), 8-bit fine offset Each channel of the XRD9814B/9816B includes a adjustment (256 linear steps), 2-bit gross offset adjust- Correlated Double Sampler (CDS), Programmable ment and input signal polarity are all programmable Gain Amplifier (PGA) and channel offset adjustment. through a serial interface. PGA gain range is 1 to 10, After gain and offset adjustment, the analog inputs are and channel offset range is -300mV to 300mV for fine sequentially sampled and digitized by an accurate 14/ adjustment and additional -400mV to +200mV for 16-bit A/D converter. The analog front-end can be gross offset adjustment. The A/D Full-Scale Range configured for inverting/non-inverting input, CDS or (FSR) is programmable to 2V or 3V. sample-hold (S/H) mode, or AC/DC coupling, making the XRD9814B/9816B suitable for use in CCD, CIS and other data acquisition applications. ORDERING INFORMATION Part No. Package Type Temperature Range XRD9814BCV 48-Lead TQFP 0C to +70C XRD9816BCV 48-Lead TQFP 0C to +70C Rev. 1.00 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.comXRD9814B/9816B BSAMP VSAMP INTERNAL TIMING CONTROL ADCCLK LCLMP INSEL 10-BIT OUTSEL PROGRAMMABLE I/O CONTROL AND RED(+) PGA BUFFERED CONFIGURATION SDI CDS or S/H RED(-) REGISTERS SCLK REGISTER LOAD 10-BIT TEST1 DAC AGND1 TEST2 REGISTER AVDD1 AVDD2 10-BIT AVDD3 3-1 PROGRAMMABLE GRN(+) PGA MUX BUFFERED CDS or S/H GRN(-) REGISTER SGND VREF 10-BIT 1.24V DAC OEB AGND2 REGISTER REFIN DB<13:0> or 14/16-BIT A/D DB<15:0> 14/16 10-BIT VREF- VREF+ PROGRAMMABLE BLU(+) PGA BUFFERED CAPP CDS or S/H BLU(-) REGISTER CAPN 10-BIT DAC CREF VCLAMP DVDD (Internal) REGISTER DGND Figure 1. Block Diagram Rev. 1.00 2 OUTPUT PORT