XRT5683AID-F MaxLinear

XR-T5683A PCM Line TM Interface Chip ...the analog plus company June 1997-3 FEATURES TTL Compatible Interface Device Can Be Used as a Line Interface Unit With- Single 5V Supply out Clock Recovery Receiver Input Can Be Either Balanced or APPLICATIONS Unbalanced T1, T2, E1 & E2 Rates, PCM Line Interface Up To 8.448Mbps Operation In Both Tx and Rx Directions Network Multiplexing and Terminating Equipment GENERAL DESCRIPTION The XR-T5683A is a PCM line interface chip consisting of attenuated by -10dB cable loss at one-half the bit rate. At both transmit and receive circuitry. This device is offered nominal supply voltage operation, the typical current in a plastic dual in-line (PDIP) or in a surface mount consumption is 40mA. package (SOIC). The maximum bit rate of the chip is 8.448Mbps, and the signal level to the receiver can be ORDERING INFORMATION Operating Part No. Package Temperature Range XR-T5683AIP 18 Lead 300 Mil PDIP -40C to +85C XR-T5683AID 18 Lead 300 Mil JEDEC SOIC -40C to +85C BLOCK DIAGRAM 1 PDC Positive Threshold Comparator TTLBuffer 11 RPOS RXDATA+ 2 TTLBuffer Peak 8 RCLK Detector RXDATA- Negative 3 Threshold 4 TE Comparator TTLBuffer 10 RNEG 6 TANK BIAS BIAS 9 RV CC BIAS 5 BIAS RGND 7 TV CC 18 Open Collector Driver TPOS 17 13 TXDATA+ TCLK 16 15 TXDATA- 12 TNEG Open Collector Driver TGND 14 Figure 1. Block Diagram Rev. 2.01 1995 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 1XR-T5683A PIN CONFIGURATION PDC 1 18 TV PDC 1 18 TV CC CC RXDATA+ 2 17 2 17 TPOS RXDATA+ TPOS 16 RXDATA- 3 3 16 TCLK RXDATA- TCLK TE 4 15 TE 4 15 TXDATA- TXDATA- 5 14 5 14 BIAS BIAS TGND TGND 6 13 TANK BIAS 6 13 TANK BIAS TXDATA+ TXDATA+ RGND 7 12 TNEG RGND 7 12 TNEG RCLK 8 11 RPOS RCLK 8 11 RPOS RV RV 9 10 RNEG 9 10 CC RNEG CC 18 Lead PDIP (0.300) 18 Lead SOIC (JEDEC, 0.300) PIN DESCRIPTION Pin Symbol Type Description 1 PDC Peak Detector Capacitor. This pin should be connected to a 0.1F capacitor. 2 RXDATA+ I Receive Analog Input Positive. Line analog input. 3 RXDATA- I Receive Analog Input Negative. Line analog input. 4 TE O Tank Excitation Output. This output connects to one side of the tank circuitry. 5 BIAS O Bias. This output is to be connected to the center tap of the receive transformer. 6 TANK BIAS O Tank Bias. The tank circuitry is biased via this output. 7 RGND Receiver Ground. To minimize ground interference a separate pin is used to ground the receive section. 8 RCLK O Recovered Receive Clock. Recovered clock signal to the terminal equipment. 9 RV Receive Supply Voltage. 5V supply voltage to the receive section. CC 10 RNEG O Receive Negative Data. Negative pulse data output to the terminal equipment (active low). 11 RPOS O Receive Positive Data. Positive pulse data output to the terminal equipment (active low). 12 TNEG I Transmit Negative Data. TNEG is valid while TCLK is high. 13 TXDATA+ O Transmit Positive Output. Transmit bipolar signal is driven to the line via a transformer. 14 TGND Transmit Ground. 15 TXDATA- O Transmit Negative Output. Transmit bipolar signal is driven to the line via a transformer. 16 TCLK I Transmit Clock. Timing element for TPOS and TNEG. 17 TPOS I Transmit Positive Data. TPOS is valid while TCLK is high. 18 TV Transmit Supply Voltage. 5V supply voltage to the transmit section. CC Rev. 2.01 2