DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTER- IDT82V2082 FACE UNIT FEATURES: Dual channel T1/E1/J1 long haul/short haul line interfaces - Receiver or transmitter power down Supports HPS (Hitless Protection Switching) for 1+1 protection - High impedance setting for line drivers without external relays - PRBS (Pseudo Random Bit Sequence) generation and detection 15 Receiver sensitivity exceeds -36 dB 772KHz and -43 dB 1024 with 2 -1 PRBS polynomials for E1 KHz - QRSS (Quasi Random Sequence Signals) generation and detection Programmable T1/E1/J1 switchability allowing one bill of ma- 20 with 2 -1 QRSS polynomials for T1/J1 terial for any line condition - 16-bit BPV (Bipolar Pulse Violation) / Excess Zero/ PRBS or QRSS Single 3.3 V power supply with 5 V tolerance on digital interfaces error counter Meets or exceeds specifications in - Analog loopback, Digital loopback, Remote loopback and Inband - ANSI T1.102, T1.403 and T1.408 loopback - ITU I.431, G.703, G.736, G.775 and G.823 Cable attenuation indication - ETSI 300-166, 300-233 and TBR12/13 Adaptive receive sensitivity - AT&T Pub 62411 Non-intrusive monitoring per ITU G.772 specification Software programmable or hardware selectable on: Short circuit protection and internal protection diode for line - Wave-shaping templates for short haul and long haul LBO (Line Build drivers Out) LOS (Loss Of Signal) and AIS (Alarm Indication Signal) detection - Line terminating impedance (T1:100 , J1:110 , E1: 75 /120 ) JTAG interface - Adjustment of arbitrary pulse shape Supports serial control interface, Motorola and Intel Non-Multi- - JA (Jitter Attenuator) position (receive path or transmit path) plexed interfaces and hardware control mode - Single rail/dual rail system interfaces Pin compatible to 82V2042E T1/E1/J1 Short Haul LIU and - B8ZS/HDB3/AMI line encoding/decoding 82V2052E E1 Short Haul LIU - Active edge of transmit clock (TCLK) and receive clock (RCLK) Available in 80-pin TQFP and 81-pin FPBGA - Active level of transmit data (TDATA) and receive data (RDATA) Green package options available DESCRIPTION: The IDT82V2082 can be configured as a dual channel T1, E1 or J1 Line the chip, and different types of loopbacks can be set according to the appli- Interface Unit. In receive path, an Adaptive Equalizer is integrated to cations. Four different kinds of line terminating impedance, 75 ,100 , remove the distortion introduced by the cable attenuation. The IDT82V2082 110 and 120 are selectable on a per channel basis. The chip also pro- also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and vides driver short-circuit protection and internal protection diode and sup- detects and reports the LOS conditions. In transmit path, there is an AMI/ ports JTAG boundary scanning. The chip can be controlled by either B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter software or hardware. Attenuator, which can be placed in either the receive path or the transmit The IDT82V2082 can be used in LAN, WAN, Routers, Wireless Base path. The Jitter Attenuator can also be disabled. The IDT82V2082 supports Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, both Single Rail and Dual Rail system interfaces. To facilitate the network CSU/DSU equipment, etc. maintenance, a PRBS/QRSS generation/detection circuit is integrated in .IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 May 4, 2009 DSC-6229/7IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT FUNCTIONAL BLOCK DIAGRAM One of the Two Identical Channels LOSn LOS/AIS Detector Receiver RCLKn Data and Adaptive RTIPn B8ZS/ Data Jitter Internal RDn/RDPn Clock Equalizer HDB3/AMI Slicer Attenuator Recovery Termination RRINGn CVn/RDNn Decoder PRBS Detector Remote Analog Digital Loopback Loopback IBLC Detector Loopback TCLKn TTIPn B8ZS/ Transmitter Jitter Line Waveform TDn/TDPn HDB3/AMI Internal Attenuator Driver TRINGn Shaper/LBO TDNn Decoder Termination PRBS Generator IBLC Generator TAOS Clock Register JTAG TAP Software Control Interface Pin Control Generator Files G.772 Monitor VDDIO VDDD VDDA VDDT VDDR Figure-1 Block Diagram FUNCTIONAL BLOCK DIAGRAM 2 May 4, 2009 MCLK INT CS SDO SCLK R/W/WR/SDI RD/DS/SCLKE A 5:0 D 7:0 MODE 1:0 TERMn RXTXM 1:0 PULSn 3:0 EQn PATTn 1:0 JA 1:0 MONTn LPn 1:0 THZ RCLKE RPDn RST TRST TCK TMS TDI TDO