WAN PLL WITH SINGLE REFERENCE INPUT IDT82V3001A FEATURES Attenuates wander from 2.1 Hz Supports AT&T TR62411 and Telcordia GR-1244-CORE Stra- Fast Lock mode tum 4 Enhanced and Stratum 4 timing for DS1 interfaces Provides Time Interval Error (TIE) correction Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 tim- MTIE of 600 ns ing for E1 interface JTAG boundary scan Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048 Holdover status indication MHz Freerun status indication Provides eight types of clock signals: C1.5o, C3o, C2o, C4o, Normal status indication C6o, C8o, C16o and C32o Lock status indication Provides six types of 8 kHz framing pulses: F0o, F8o, F16o, 3.3 V operation with 5 V tolerant I/O F32o, RSP and TSP Package available: 56-pin SSOP (Green option available) Holdover frequency accuracy of 0.025 ppm Phase slope of 5 ns/125 s DESCRIPTION The IDT82V3001A is a WAN PLL with single reference input. It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/ contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS wander, frequency accuracy, capture range, phase change slope, clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 holdover frequency accuracy and MTIE (Maximum Time Interval Error) MHz or 8 kHz input reference. requirements for these specifications. The IDT82V3001A provides eight types of clock signals (C1.5o, C3o, The IDT82V3001A can be used in synchronization and timing control C6o, C2o, C4o, C8o, C16o, C32o) and six types of framing signals (F0o, for T1 and E1 systems, or used as ST-BUS clock and frame pulse F8o, F16o, F32o, RSP, TSP) for the multitrunk T1 and E1 primary rate sources. It can also be used in access switch, access routers, ATM edge transmission links. switches, wireless base station controllers, or IADs (Integrated Access The IDT82V3001A is compliant with AT&T TR62411, Telcordia GR- Devices), PBXs and line cards. 1244-CORE Stratum 4 Enhanced and Stratum 4, ETSI ETS 300 011. It IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 November 14, 2012 2006 Integrated Device Technology, Inc. DSC-6242/4IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT FUNCTIONAL BLOCK DIAGRAM V V V V V V V V V V OSCi OSCo DDA TCLR DDA SS SS DDD SS DDD SS DDD SS C32o OSC C16o Virtual C8o TIE Control Reference Fref C4o Block C2o C3o C1.5o FLOCK DPLL C6o TDI F0o F8o TMS Invalid Input F16o JTAG TRST Signal F32o TCK Detection RSP TDO TSP Feedback Signal LOCK RST Input Frequency State Control Circuit Selection TIE en MODE sel1 MODE sel0 NORMAL HOLDOVER FREERUN F sel1 F sel0 Figure - 1 Block Diagram FUNCTIONAL BLOCK DIAGRAM 2 November 14, 2012