Short Form Data Sheet
April 2012
MAX24188
Low-Cost IEEE 1588 Clock
General Description Highlighted Features
The MAX24188 is a flexible, low-cost IEEE 1588
Complete Hardware Support for IEEE 1588
clock designed to be the central 1588 time base in a
Flexible Block for Any 1588 Architecture
multiport system. In such systems (typically boundary
Enables Ordinary, Boundary, and Transparent
clocks or transparent clocks) timestampers at the
Clocks
ports must all have a common time and frequency
reference. The MAX24188 serves as that common
Steered by Software to Follow an External 1588
reference. As the system exchanges 1588 packets
Master
with an external 1588 master and calculates its time
-8 -32
2 ns Time Resolution and 2 ns Period Resolution
offset vs. the master, the MAX24188 can be adjusted
by system software to zero out the time offset and
1ns Input Timestamp Accuracy and Output Edge
thereby achieve time and frequency synchronization
Placement Accuracy
with the master. As the MAX24188 is adjusted, its
Three Time/Frequency Controls: Direct Time
output frequency and time alignment signals are
Write, Time Adjustment, and High-Resolution
correspondingly adjusted. All timestampers (and
Frequency Adjustment
other time-aware components) that receive those
Programmable Clock and Time-Alignment I/O to
signals then follow the adjustment to maintain
Synchronize All 1588 Elements in the System
synchronization with the MAX24188. In this way all
1588 elements in the system maintain a common
Can Provide an Output Clock Signal to Slave
sense of time and frequency.
Components (125MHz/N, 1 N 255)
Can Provide an Output Time Alignment Signal
The MAX24188 can be a standalone central timing
to Slave Components (e.g., 1PPS)
function for 1588 systems. It can also be used in
Can Frequency-Lock to an Input Clock Signal
conjunction with one of Maxims clock
from Elsewhere in the System
synchronization ICs in multimode systems designed
Can Timestamp an Input Time Alignment
to be clocked by 1588, 1588 plus frequency (such as
Signal to Time-Lock to a Master Elsewhere in
synchronous Ethernet), or frequency only.
the System (e.g., 1PPS)
Applications
Input Event Timestamper Detects Incoming
Time Alignment (e.g., 1PPS) or Clock Edges,
Central Time-Clock for 1588-Enabled Equipment with
Can Timestamp Rising and/or Falling Edges
Timestamping on Multiple Ports
Flexible Programmable Event Generator (PEG)
Wireless Base Stations and Controllers
Can Output 1PPS (One Pulse per Period) or a
Switches, Routers, DSLAMs, PON Equipment
Pseudowire Circuit Emulation Equipment Wide Variety of Clock Signals
Test and Measurement Systems
Built-In Support for Telecom Equipment Timing
Medical, Industrial, and Factory Automation Equipment
Architectures with Dual Redundant Timing Cards
Ordering Information
Full Support to Enable Switches and Routers to
Be Transparent Clocks and/or Boundary Clocks
PART TEMP RANGE PIN-PACKAGE
Full Support for 1588 and Synchronous Ethernet
MAX24188ETK+ -40C to +85C 68 TQFN-EP*
Operates from a 10MHz, 12.8MHz, 25MHz, or
+Denotes a lead-free/RoHS-compliant package.
125MHz Reference Clock
*EP = Exposed pad.
SPI Processor Interface
SPI is a trademark of Motorola, Inc.
1.2V Operation with 3.3V I/O
1 Short Form Data Sheet
MAX24188
Application Examples
Example 1: Multiport System with Central 1588 Software
TS TS
Central
Ethernet Ports Ethernet Ports
Line Card 1 Line Card N
Switching
TS TS
Function
Example: DS31400.
Optional. Can provide
Example: MAX24288
Processor
holdover, clock selection
and frequency translation.
1588 SW
Optional: 1PPS MAX24188 Clock Sync system clock
from GPS receiver e.g. 25MHz
1588 Clock Function
1588 time alignment, e.g. 1 PPS
Example 2: Multiport System with Distributed 1588 Software
TS TS
Line Card 1 Line Card N
Central
Ethernet Ports Ethernet Ports
uP uP
Switching
TS 1588 SW 1588 SW TS
Function
Example: DS31400.
Optional. Can provide
Example: MAX24288 Processor
holdover, clock selection
1588 SW and frequency translation.
Optional: 1PPS MAX24188 Clock Sync system clock
from GPS receiver e.g. 25MHz
1588 Clock Function
1588 time alignment, e.g. 1 PPS
Block Diagram
MAX24188
Reference
125MHz, 8 phases
Clock PLL REFCLK
RST_N
time
125MHz
Control
CS_N
SCLK and
SDI 1588
TS1 TS2 TS3 PEG1 PEG2 Output
Status
SDO
Time Time Time Prog. Event Prog. Event Clock Time
Generator
Stamper Stamper Stamper Generator Generator
Engine
JTRST_N
JTAG GPIO Control
2
JTCLK
JTMS
JTDI
JTDO
GPO1
GPO2
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7