Ethernet Clock Generator, 10 Clock Outputs AD9571 FEATURES FUNCTIONAL BLOCK DIAGRAM REFSEL Fully integrated VCO/PLL core 0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz CMOS 0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz XTAL Input crystal or clock frequency of 25 MHz OSC 6 25MHz Preset divide ratios for 156.25 MHz, 33.33 MHz,100 MHz, and REFCLK 125 MHz PFD/CP Choice of LVPECL or LVDS output format Integrated loop filter 3RD-ORDER 6 copies of reference clock output LPF Rates configured via strapping pins Space saving 6 mm 6 mm 40-lead LFCSP LVPECL OR VCO LVDS 0.48 W power dissipation (LVDS operation) 1 156.25MHz 0.69 W power dissipation (LVPECL operation) 3.3 V operation 2 100MHz OR 125MHz APPLICATIONS CMOS Ethernet line cards, switches, and routers 1 33.33MHz SCSI, SATA, and PCI-express FORCE LOW PCI support included AD9571 Low jitter, low phase noise clock generation FREQSEL Figure 1. GENERAL DESCRIPTION feedback divider and output divider. By connecting an external The AD9571 provides a multioutput clock generator function crystal or reference clock to the REFCLK pin, frequencies up to comprising a dedicated PLL core that is optimized for Ethernet 156.25 MHz can be locked to the input reference. line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low Each output divider and feedback divider ratio is prepro- jitter frequency synthesizers to maximize network performance. grammed for the required output rates. No external loop filter Other applications with demanding phase noise and jitter components are required, thus conserving valuable design time requirements also benefit from this part. and board space. The PLL section consists of a low noise phase frequency The AD9571 is available in a 40-lead 6 mm 6 mm lead frame detector (PFD), a precision charge pump (CP), a low phase chip scale package and can be operated from a single 3.3 V noise voltage controlled oscillator (VCO), and a preprogrammed supply. The operating temperature range is 40C to +85C. OPTIONAL CPU CX-4 PHY ISLAND XAUI 6 25MHz 2 125MHz 48 + 2 SWITCH/MAC 1 156.25MHz AD9571 1 33.33MHz 2 OCTAL 2 OCTAL 2 OCTAL 2 OCTAL GbE PHY GbE PHY GbE PHY GbE PHY Figure 2. Typical Application Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 07499-002 DIVIDERS 07499-001AD9571 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................9 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions ............................10 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ............................................12 General Description ......................................................................... 1 Terminology .....................................................................................13 Revision History ............................................................................... 2 Theory of Operation .......................................................................14 Specifications ..................................................................................... 3 Outputs .........................................................................................14 PLL Characteristics ...................................................................... 3 Phase Frequency Detector (PFD) and Charge Pump.............15 LVDS Clock Output Jitter ............................................................ 4 Power Supply ................................................................................15 LVPECL Clock Output Jitter ....................................................... 5 CMOS Clock Distribution .........................................................15 CMOS Clock Output Jitter .......................................................... 5 LVPECL Clock Distribution ......................................................16 Reference Input ............................................................................. 5 LVDS Clock Distribution ...........................................................16 Clock Outputs ............................................................................... 6 Reference Input............................................................................16 Timing Characteristics................................................................. 6 Power and Grounding Considerations and Power Supply Rejection .......................................................................................16 Control Pins .................................................................................. 7 Outline Dimensions ........................................................................17 Power .............................................................................................. 7 Ordering Guide............................................................................17 Crystal Oscillator .......................................................................... 7 Timing Diagrams.......................................................................... 8 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 REVISION HISTORY 8/09Revision 0: Initial Version Rev. 0 Page 2 of 20