601G-01ILF Renesas

DATASHEET LOW PHASE NOISE CLOCK MULTIPLIER ICS601-01 Description Features The ICS601-01 is a low-cost, low phase noise, Packaged in 16-pin SOIC or TSSOP high-performance clock synthesizer for applications Pb (lead) free package which require low phase noise and low jitter. It is IDTs Uses fundamental 10 - 27 MHz crystal or clock lowest phase noise multiplier, and also the lowest CMOS part in the industry. Using IDTs patented Patented PLL with the lowest phase noise analog and digital Phase-Locked Loop (PLL) Output clocks up to 156 MHz at 3.3 V techniques, the chip accepts a 10 - 27 MHz crystal or Low phase noise: -132 dBc/Hz at 10 kHz clock input, and produces output clocks up to 156 MHz at 3.3 V. Low jitter - 18 ps one sigma typ. Full swing CMOS outputs with 25 mA drive capability This product is intended for clock generation. It has low at TTL levels output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. Advanced, low power, sub-micron CMOS process For applications which require definted input to output Industrial temperature range available timing, use the ICS670-01. Operating voltage of 3.3V or 5V Block Diagram VDD 3 Reference Phase Charge Loop VCO CLK Divider Comparator Pump Filter X1/ICLK VCO Crystal Divide Oscillator Crystal or X2 clock input REFOUT ROM Based Multipliers 4 3 OE REFEN S3:0 GND IDT / ICS LOW PHASE NOISE CLOCK MULTIPLIER 1 ICS601-01 REV N 051310ICS601-01 LOW PHASE NOISE CLOCK MULTIPLIER CLOCK MULTIPLIER Pin Assignment Multiplier Select Table S3 S2 S1 S0 CLK (see note 2 on following page) CLK 1 16 GND 00 0 0 TEST 2 REFEN 15 GND 00 0 1 TEST VDD 3 14 GND 00 10 Input x1 VDD 4 13 REFOUT VDD 5 12 OE 00 11 Input x3 X2 6 11 S0 01 00 Input x4 S1 7 10 S3 01 01 Input x5 X1/ICLK 8 9 S2 01 10 Input x6 01 11 Input x8 16 Pin (150 mil) TSSOP or SOIC 10 0 0 TEST 10 0 1 Crystal osc. pass through (no PLL) 10 10 Input x2 10 1 1 TEST 11 00 Input x8 11 0 1 Input x10 11 1 0 Input x12 11 1 1 Input x16 0 = connect directly to ground 1 = connect directly to VDD Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 CLK Output Clock output from VCO. Output frequency equals the input frequency times multiplier. 2 REFEN Input Reference clock enable. Turns off the buffered crystal oscillator clock (stops low) when low. 3 VDD Power Connect to +3.3V or +5V. Must match other VDDs. 4 VDD Power Connect to +3.3V or +5V. Must match other VDDs. 5 VDD Power Connect to +3.3V or +5V. Must match other VDDs. 6 X2 XO Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal. Leave disconnected for an external clock input. 7 S1 Input Multiplier select pin 1. Determines CLK output per table above. Internal pull-up. 8 X1/ICLK XI Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal or clock. 9 S2 Input Multiplier select pin 2. Determines CLK output per table above. Internal pull-up. 10 S3 Input Multiplier select pin 3. Determines CLK output per table above. Internal pull-up. 11 S0 Input Multiplier select pin 0. Determines CLK output per table above. Internal pull-up. 12 OE Input Output Enable. Tri-states both output clocks when low. Internal pull-up. 13 REFOUT Output Buffered crystal oscillator clock output. Controlled by REFIN. 14 - 16 GND Power Connect to ground. IDT / ICS LOW PHASE NOISE CLOCK MULTIPLIER 2 ICS601-01 REV N 051310