3.3 V/5 VECL 2/4, 4/5/6 Clock Generation Chip MC10EP139, MC100EP139 Description The MC10/100EP139 is a low skew 2/4, 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The www.onsemi.com internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on 1 1 the internal clock when the device is enabled/disabled as can happen with SOIC20 WB an asynchronous control. The internal enable flip-flop is clocked on the TSSOP20 WB DT SUFFIX DW SUFFIX falling edge of the input clock, therefore, all associated specification CASE 948E CASE 751D limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state therefore the master reset (MR) input may require assertion to ensure MARKING DIAGRAMS* system synchronization. Internal divider design ensures synchronization between the 2/4 and the 4/5/6 outputs within a device. All V and CC 20 V pins must be externally connected to power supply to guarantee EE HEP or KEP MCXXXEP139 139 proper operation. AWLYYWWG ALYW The V Pin, an internally generated voltage supply, is available to this BB device only. For Single-Ended input conditions, the unused differential 1 input is connected to V as a switching reference voltage. V may also BB BB TSSOP20 WB SOIC20 WB rebias AC coupled inputs. When used, decouple V and V via a BB CC 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When HEP = MC10EP KEP = MC100EP not used, VBB should be left open. XXX = 10 or 100 The 100 Series contains temperature compensation. A = Assembly Location L,WL = Wafer Lot Features Y, YY = Year Maximum Frequency = > 1.0 GHz Typical W, WW = Work Week G or = Pb-Free Package 50 ps Output-to-Output Skew PECL Mode Operating Range: (Note: Microdot may be in either location) V = 3.0 V to 5.5 V with V = 0 V CC EE *For additional marking information, refer to Application Note AND8002/D. NECL Mode Operating Range: V = 0 V with V = 3.0 V to 5.5 V CC EE Open Input Default State ORDERING INFORMATION Safety Clamp on Inputs Device Shipping Package Synchronous Enable/Disable MC10EP139DTG TSSOP20 WB 75 Units / Master Reset for Synchronization of Multiple Chips Tube (Pb-Free) V Output 75 Units / BB MC100EP139DTG TSSOP20 WB Tube (Pb-Free) These Devices are Pb-Free, Halogen Free and are RoHS Compliant MC100EP139DTR2G TSSOP20 WB 2500 / (Pb-Free) Tape & Reel MC100EP139DWG TSSOP20 WB 38 Units / (Pb-Free) Tube For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifica- tions Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: April, 2021 Rev. 15 MC10EP139/DMC10EP139, MC100EP139 V Table 1. PIN DESCRIPTION 1 20 CC V CC PIN FUNCTION EN 2 19 Q0 CLK*, CLK* ECL Differential Clock Inputs DIVSELb0 3 18 Q0 EN* ECL Sync Enable CLK 4 17 Q1 MR* ECL Master Reset CLK 5 16 Q1 MC10/100EP139 V ECL Reference Output BB V BB 6 15 Q2 Q0, Q1, Q0, Q1 ECL Differential 2/4 Outputs MR 14 7 Q2 Q2, Q3, Q2, Q3 ECL Differential 4/5/6 Outputs V CC Q3 8 13 DIVSELa* ECL Frequency Select Input 2/4 DIVSELb1 9 12 Q3 DIVSELb0* ECL Frequency Select Input 4/5/6 V DIVSELa EE 11 10 DIVSELb1* ECL Frequency Select Input 4/5/6 V ECL Positive Supply CC Warning: All V and V pins must be externally connected to CC EE a Power Supply to guarantee proper operation. V ECL Negative Supply EE Figure 1. 20-Lead Pinout (Top View) *Pins will default low when left open. DIVSELa Q0 CLK 2/4 Q0 R CLK Q1 Q1 Q2 EN 4/5/6 Q2 R Q3 MR Q3 DIVSELb0 DIVSELb1 V EE Figure 2. Logic Diagram Table 2. FUNCTION TABLES CLK EN MR Function Z L L Divide ZZ H L Hold Q0:3 X X H Reset Q0:3 Z = Low-to-High Transition ZZ = High-to-Low Transition DIVSELa Q0:1 Outputs L Divide by 2 H Divide by 4 DIVSELb0 DIVSELb1 Q2:3 Outputs L L Divide by 4 H L Divide by 6 L H Divide by 5 H H Divide by 5 www.onsemi.com 2