T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS IDT82V3010 FEATURES Phase slope of 5 ns per 125 s Supports AT&T TR62411 Attenuates wander from 2.1 Hz Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing Fast lock mode for E1 interface Provides Time Interval Error (TIE) correction Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or MTIE of 1 s 19.44 MHz JTAG boundary scan Accepts two independent reference inputs which may have Holdover status indication same or different nominal frequencies applied to them Freerun status indication Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o and C32o Normal status indication output clock signals Lock status indication Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o, Input reference quality indication F32o, RSP and TSP 3.3 V operation with 5 V tolerant I/O Provides a C2/C1.5 output clock signal with the frequency Package: 56-pin SSOP (Green option available) controlled by the selected reference input Fref0 or Fref1 FUNCTIONAL BLOCK DIAGRAM TDO TDI OSCi TCLR RST V V V V V V V V V V DDD SS DDD SS DDD SS DDA SS DDA SS C2/C1.5 TCK C32o C19o TMS JTAG OSC C19POS TRST C19NEG Virtual C16o Reference Input TIE Control Fref0 Reference C8o Switch Block Fref1 C4o C2o IN sel C3o DPLL FLOCK C1.5o C6o F0o Reference Input MON out0 F8o Monitor 0 F16o F19o Feedback Signal Reference Input F32o MON out1 Monitor 1 RSP TSP LOCK Invalid Input Signal Detection F0 sel0 Frequency Select Circuit 0 F0 sel1 State Control Circuit F1 sel0 Frequency Select Circuit 1 F1 sel1 TIE en MODE sel1 MODE sel0 Normal Holdover Freerun IDT and IDT logo are trademarks of Integrated Device Technology, Inc. 1 November 14, 2012 2006 Integrated Device Technology, Inc. DSC-6777/2IDT82V3010 T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs DESCRIPTION The IDT82V3010 is a T1/E1/OC3 telecom clock generator with dual 300 011. It meets the jitter/wander tolerance, jitter/wander transfer, reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which intrinsic jitter/wander, frequency accuracy, capture range, phase change generates low jitter ST-BUS and 19.44 MHz clock and framing signals slope, holdover frequency accuracy and MTIE (Maximum Time Interval that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz Error) requirements for these specifications. input reference. The IDT82V3010 can be used in synchronization and timing control The IDT82V3010 provides 9 types of clock signals (C1.5o, C3o, C6o, for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o, source. It also can be used in access switch, access routers, ATM edge F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3 switches, wireless base station controllers, or IADs (Integrated Access links. Devices), PBXs, line cards and SONET/SDH equipments. The IDT82V3010 is compliant with AT&T TR62411 and ETSI ETS PIN CONFIGURATION MODE sel0 1 TIE en 56 MODE sel1 2 IC2 55 3 54 C2/C1.5 TCLR 4 53 IC0 RST 5 Fref0 HOLDOVER 52 6 Fref1 51 FREERUN 7 MON out0 50 OSCi 8 49 MON out1 F19o 9 VDDA F0 sel0 48 F0 sel1 10 47 VSS IN sel 11 46 NORMAL 12 VSS 45 FLOCK VDDD 13 LOCK 44 14 43 C19o C6o IDT82V3010 C1.5o 15 42 TSP 16 41 RSP C3o C2o 17 40 F32o VSS 18 39 F16o 19 VDDD VSS 38 20 37 VDDA C4o C19POS 21 36 F8o 22 35 F1 sel0 C19NEG 23 C8o 34 F1 sel1 24 33 C16o F0o 32 TDI C32o 25 VDDD 26 31 TMS VSS 27 30 TRST 28 29 TCK TDO Figure - 1 IDT82V3010 SSOP56 Package Pin Assignment Description 2 November 14, 2012