XRT6166CD-F MaxLinear

XR-T6166 Codirectional Digital Data TM Processor ...the analog plus company Dec 2010 APPLICATIONS FEATURES CCITT G.703 Compliant 64kbps Codirectional Low Power CMOS Technology Interface All Receiver and Transmitter Inputs and Outputs are Performs the Digital and Analog Functions for TTL Compatible a Complete 64kbps Data Adaption Unit (DAU) When Transmitter Inhibits Bipolar Violation Insertion for Used With the XR-T6164 Transmission of Alarm Conditions Alarm Output Indicates Loss of Received Bipolar Violations Tolerance of 125s Variance of Data Transfer Timing in Both Transmit and Receive Paths Allows Operation in Plesiochronous Networks Both Receiver and Transmitter Perform Byte Insertion or Deletion in Response to Local Clock Slips and Provide Outputs Indicating Slip Logic Activity GENERAL DESCRIPTION The XR-T6166 is a CMOS device which contains the stream. The receiver , which performs the reverse digital circuitry necessary to interface both directions of a operation, decodes the 64kbps data, extracts a clock 64kbps data stream to 2.048Mbps transmit and receive signal, and then outputs the data to a 2.048Mbps PCM time-slots. The XR-T6166 and the companion time-slot. The XR-T6166 provides features which allow XR-T6164 line interface chip together form a CCITT the repetitions and deletions of both received and G.703 compliant 64kbps codirectional interface. transmitted data as clock skews and transients occur . These slip occurrences are indicated by byte insertion The XR-T6166 contains separate transmit and receive and deletion flags. Outputs are also provided for sections. The transmitter transforms 8 bit serial data from extracted receive clock and clock recovery circuit loss of a 2.048Mbps time-slot into an encoded 64kbps data lock. ORDERING INFORMATION Operating Part No. Package Temperature Range XR-T6166CD 28 Lead 300 Mil JEDEC SOIC 0C to +70C XR-T6166ID 28 Lead 300 Mil JEDEC SOIC 40C to 85C Rev. 2.03 2010 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 (510) 668-7010 1XR-T6166 19 PCMIN D 8 Bit Input Register 20 TX2MHz CLK Byte 8 Deletion 10 11 TS1T BDT 8 Bit Latch time-slot 12 TS2T Load Mux Byte 8 Insertion 18 15 TTSEL CLK BIT 8 Bit Output Register Load Q Control Circuitry 17 TX256kHz D Octet Violation CLK Counter Insertion Coding 13 T+R Q Logic 16 ALARMIN D CLK 14 Q T-R Figure 1. XR-T6166 Transmitter Section Block Diagram Byte Sync Violation Detection Loss 1 ALARM Alarm CLK 2 S+R Data Decoder S-R 3 CLK BLS 4 D Q 8 Bit Reg 0 28 PCMOUT 5 RX2MHz CLK Register time-slot Select Mux Logic TS1R 23 D Q 8 Bit Reg 1 Time CLK 24 Slot TS2R REG 0 SEL Mux REG 1 SEL Byte BIR 26 Insertion RTSEL 27 time-slot Byte 25 BDR Deletion 6 BLANK 128kHz Recovered Clock 7 RXCKOUT Clock Recovery 9 RXCK2MHz 22 CS Figure 2. XR-T6166 Receiver Section Block Diagram Rev. 2.03 2