xxrr XRT75R03 xxrr THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR MARCH 2006 REV. 1.0.8 TRANSMITTER: GENERAL DESCRIPTION 3 R Technology (Reconfigurable, Relayless The XRT75R03 is a three-channel fully integrated Redundancy) 3 Line Interface Unit (LIU) featuring EXARs R Technology (Reconfigurable, Relayless Redundancy) Compliant with Bellcore GR-499, GR-253 and ANSI with Jitter Attenuator for E3/DS3/STS-1 applications. T1.102 Specification for transmit pulse It incorporates 3 independent Receivers, Tri-state Transmit output capability for redundancy Transmitters and Jitter Attenuators in a single 128 pin applications LQFP package. Each Transmitter can be independently turned on Each channel of the XRT75R03 can be or off independently configured to operate in the data rate, E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 Transmitters provide Voltage Output Drive MHz). Each transmitter can be turned off and tri- JITTER ATTENUATOR: stated for redundancy support or for conserving power. On chip advanced crystal-less Jitter Attenuator for each channel The XRT75R03s differential receiver provides high noise interference margin and is able to receive the Jitter Attenuator can be selected in Receive or data over 1000 feet of cable or with up to 12 dB of Transmit paths cable attenuation. Meets ETSI TBR 24 Jitter Transfer Requirements The XRT75R03 incorporates an advanced crystal- Compliant with jitter transfer template outlined in less jitter attenuator per channel that can be selected ITU G.751, G.752, G.755 and GR-499-CORE,1995 either in the transmit or receive path. The jitter standards attenuator performance meets the ETSI TBR-24 and Bellcore GR-499 specifications. 16 or 32 bits selectable FIFO size The XRT75R03 provides both Serial Microprocessor Jitter Attenuator can be disabled Interface as well as Hardware mode for programming CONTROL AND DIAGNOSTICS: and control. The XRT75R03 supports local, remote and digital 5 wire Serial Microprocessor Interface for control loop-backs. The device also has a built-in Pseudo and configuration Random Binary Sequence (PRBS) generator and Supports optional internal Transmit driver detector with the ability to insert and detect single bit monitoring error for diagnostic purposes. Hardware Mode for control and configuration FEATURES Each channel supports Local, Remote and Digital RECEIVER: Loop-backs 3 Single 3.3 V 5% power supply R Technology (Reconfigurable, Relayless Redundancy) 5 V Tolerant digital inputs On chip Clock and Data Recovery circuit for high Available in 128 pin LQFP input jitter tolerance - 40C to 85C Industrial Temperature Range Meets E3/DS3/STS-1 Jitter Tolerance Requirement APPLICATIONS Detects and Clears LOS as per G.775 E3/DS3 Access Equipment Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation DSLAMs On chip B3ZS/HDB3 encoder and decoder that can Digital Cross Connect Systems be either enabled or disabled CSU/DSU Equipment On-chip clock synthesizer provides the appropriate Routers rate clock from a single 12.288 MHz Clock Fiber Optic Terminals Provides low jitter output clock Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT75R03 xxrr xxrr REV. 1.0.8 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR FIGURE 1. BLOCK DIAGRAM OF THE XRT 75R03 SDI CLKOUT XRT75R03 SDO XRT75R03 E3Clk,DS3Clk, Serial INT STS-1Clk Processor SClk Interface RLOL (n) CS RxON RESET RxClkINV Clock HOST/HW Invert RxClk (n) Synthesizer Peak Detector STS-1/DS3 (n) E3 (n) HDB3/ RPOS (n) REQEN (n) Clock & Data Jitter Slicer B3ZS AGC/ MUX RNEG (n)/ RTIP (n) Recovery Attenuator Equalizer Decoder LCV (n) RRing (n) LOS SR/DR Remote Detector Local LLB (n) LoopBack RLB (n) LoopBack RLOS (n) LOSTHR JATx/Rx TTIP (n) TPData (n) HDB3/ Line Tx Jitter Timing B3ZS Driver MUX TNData (n) Pulse Attenuator TRing (n) Encoder Control Shaping TxClk (n) TAOS (n) MTIP (n) Device MRing (n) Tx TxLEV (n) Monitor Control TxON (n) Channel 0 DMO (n) Channel 1 Channel 2 Notes: 1. (n) = 0, 1 or 2 for respective Channels 2. Serial Processor Interface input pins are shared by the three Channels inHos Mode and redefined in theHardwar Mode. TRANSMIT INTERFACE CHARACTERISTICS Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the line Integrated Pulse Shaping Circuit Built-in B3ZS/HDB3 Encoder (which can be disabled) Accepts Transmit Clock with duty cycle of 30%-70% Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and ANSI T1.102 1993 Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE Transmitter can be turned off in order to support redundancy designs RECEIVE INTERFACE CHARACTERISTICS Integrated Adaptive Receive Equalization (optional) for optimal Clock and Data Recovery Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications Meets Jitter Tolerance Requirements, as specified in ITU-T G.823 1993 for E3 Applications Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms Built-in B3ZS/HDB3 Decoder (which can be disabled) Recovered Data can be muted while the LOS Condition is declared Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment 2