XRT75R06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER DECEMBER 2004 REV. 1.0.0 Bellcore GR-499 specifications. Also, the jitter GENERAL DESCRIPTION attenuators can be used for clock smoothing in The XRT75R06D is a six channel fully integrated Line SONET STS-1 to DS-3 de-mapping. 3 Interface Unit (LIU) featuring EXARs R Technology The XRT75R06D provides a Parallel Microprocessor (Reconfigurable, Relayless, Redundancy) for E3/ Interface for programming and control. DS3/STS-1 applications. The LIU incorporates 6 The XRT75R06D supports analog, remote and digital independent Receivers, Transmitters and Jitter loop-backs. The device also has a built-in Pseudo Attenuators in a single 217 Lead BGA package. Random Binary Sequence (PRBS) generator and Each channel of the XRT75R06D can be detector with the ability to insert and detect single bit independently configured to operate in E3 (34.368 error for diagnostic purposes. MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz). Each transmitter can be turned off and tri-stated for APPLICATIONS redundancy support or for conserving power. E3/DS3 Access Equipment The XRT75R06Ds differential receiver provides high DSLAMs noise interference margin and is able to receive data over 1000 feet of cable or with up to 12 dB of cable Digital Cross Connect Systems attenuation. CSU/DSU Equipment The XRT75R06D incorporates an advanced crystal- Routers less jitter attenuator per channel that can be selected either in the transmit or receive path. The jitter Fiber Optic Terminals attenuator performance meets the ETSI TBR-24 and FIGURE 1. BLOCK DIAGRAM OF THE XRT 75R06D CS RD XRT75R06D WR XRT75R06D CLKOUT n Addr 7:0 Processor Interface D 7:0 SFM en PCLK RDY RLOL n INT E3Clk Pmode Clock DS3Clk RESET Synthesizer Peak Detector STS-Clk/12M RxClk n HDB3/ Clock & Data Jitter AGC/ Slicer B3ZS MUX RxPOS n RTIP n Recovery Attenuator Decoder Equalizer RxNEG/LCV n RRing n LOS Remote Detector Local LoopBack LoopBack RLOS n TxClk n TTIP n HDB3/ Line Tx Jitter B3ZS TxPOS n Driver Timing MUX Pulse Attenuator TRing n Encoder Control Shaping TxNEG n MTIP n Device MRing n Tx Monitor TxON Control Channel 0 DMO n Channel n... Channel 5 ICT ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XRT75R06DIB 217 Lead BGA -40 C to +85 C Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT75R06D REV. 1.0.0 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FEATURES Each channel supports Analog, Remote and Digital Loop-backs RECEIVER Single 3.3 V 5% power supply 3 R Technology (Reconfigurable, Relayless, 5 V Tolerant digital inputs Redundancy) Available in 217 pin BGA Package On chip Clock and Data Recovery circuit for high input jitter tolerance - 40C to 85C Industrial Temperature Range Meets E3/DS3/STS-1 Jitter Tolerance Requirement TRANSMIT INTERFACE CHARACTERISTICS Detects and Clears LOS as per G.775 Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal Receiver Monitor mode handles up to 20 dB flat to the line loss with 6 dB cable attenuation Integrated Pulse Shaping Circuit On chip B3ZS/HDB3 encoder and decoder that can be either enabled or disabled Built-in B3ZS/HDB3 Encoder (which can be disabled) On-chip clock synthesizer provides the appropriate rate clock from a single 12.288 MHz Clock Accepts Transmit Clock with duty cycle of 30%- 70% Provides low jitter output clock TRANSMITTER Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications 3 R Technology (Reconfigurable, Relayless, Generates pulses that comply with the DSX-3 pulse Redundancy) template, as specified in Bellcore GR-499-CORE Compliant with Bellcore GR-499, GR-253 and ANSI and ANSI T1.102 1993 T1.102 Specification for transmit pulse Generates pulses that comply with the STSX-1 Tri-state Transmit output capability for redundancy pulse template, as specified in Bellcore GR-253- applications CORE Each Transmitter can be independently turned on Transmitter can be turned off in order to support or off redundancy designs Transmitters provide Voltage Output Drive RECEIVE INTERFACE CHARACTERISTICS JITTER ATTENUATOR Integrated Adaptive Receive Equalization (optional) On chip advanced crystal-less Jitter Attenuator for for optimal Clock and Data Recovery each channel Declares and Clears the LOS defect per ITU-T Jitter Attenuator can be selected in Receive, G.775 requirements for E3 and DS3 applications Transmit path, or disabled Meets Jitter Tolerance Requirements, as specified Meets ETSI TBR 24 Jitter Transfer Requirements in ITU-T G.823 1993 for E3 Applications Compliant with jitter transfer template outlined in Meets Jitter Tolerance Requirements, as specified ITU G.751, G.752, G.755 and GR-499-CORE,1995 in Bellcore GR-499-CORE for DS3 Applications standards Declares Loss of Lock (LOL) Alarm 16 or 32 bits selectable FIFO size Built-in B3ZS/HDB3 Decoder (which can be CONTROL AND DIAGNOSTICS disabled) Parallel Microprocessor Interface for control and Recovered Data can be muted while the LOS configuration Condition is declared Supports optional internal Transmit driver Outputs either Single-Rail or Dual-Rail data to the monitoring Terminal Equipment 2