xxrr XRT75L02 xxrr TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER DECEMBER 2005 REV. 1.0.3 GENERAL DESCRIPTION Provides low jitter clock outputs for either DS3,E3 or STS-1 rates. The XRT75L02 is a two-channel fully integrated Line On-chip clock synthesizer provides the appropriate Interface Unit (LIU) with Jitter Attenuator for E3/DS3/ rate clock from a single 12.288 MHz Clock. STS-1 applications. It incorporates independent Provides low jitter output clock. Receivers, Transmitters and Jitter Attenuators in a single 100 pin TQFP package. TRANSMITTER: The XRT75L02 can be configured to operate in either Compliant with Bellcore GR-499, GR-253 and ANSI E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 T1.102 Specification for transmit pulse MHz) modes.The transmitter can be turned off (tri- Tri-state Transmit output capability for redundancy stated) for redundancy support and for conserving applications power. Transmitters can be turned on or off. The XRT75L02s differential receiver provides high JITTER ATTENUATOR: noise interference margin and is able to receive the data over 1000 feet of cable or with up to 12 dB of On chip advanced crystal-less Jitter Attenuator. cable attenuation. Jitter Attenuator can be selected in Receive or The XRT75L02 incorporates advanced crystal-less Transmit paths. jitter attenuators that can be selected either in the 16 or 32 bits selectable FIFO size. transmit or receive path. The jitter attenuator Meets the Jitter and Wander specifications performance meets the ETSI TBR-24 and Bellcore described in T1.105.03b,ETSI TBR-24, Bellcore GR-499 specifications. GR-253 and GR-499 standards. The XRT75L02 provides both Serial Microprocessor Jitter Attenuators can be disabled. Interface as well as Hardware mode for programming CONTROL AND DIAGNOSTICS: and control. 5 wire Serial Microprocessor Interface for control The XRT75L02 supports local,remote and digital and configuration. loop-backs. The XRT75L02 also contains an on- board Pseudo Random Binary Sequence (PRBS) Supports optional internal Transmit Driver generator and detector with the ability to insert and Monitoring. detect single bit error. PRBS error counter register to accumulate errors. FEATURES Hardware Mode for control and configuration. Supports Local, Remote and Digital Loop-backs. RECEIVER: Single 3.3 V 5% power supply. On chip Clock and Data Recovery circuit for high input jitter tolerance. 5 V Tolerant I/O. Meets the jitter tolerance requirements as specified Available in 100 pin TQFP. in ITU-T G.823 1993 for E3 and Telcordia GR-499- -40C to 85C Industrial Temperature Range. CORE for DS3 applications. Detects and Clears LOS as per G.775. APPLICATIONS Receiver Monitor mode handles up to 20 dB flat E3/DS3 Access Equipment. loss with 6 dB cable attenuation. STS1-SPE to DS3 Mapper. On chip B3ZS/HDB3 encoder and decoder that can DSLAMs. either be enabled or disabled. Digital Cross Connect Systems. On-chip clock synthesizer generates the appropriate rate clock from a single frequency CSU/DSU Equipment. XTAL. Routers. Fiber Optic Terminals. Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT75L02 xxrr xxrr TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER REV. 1.0.3 FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L02 SDI CLK OUT XRT75L03 SDO Serial E3Clk,DS3Clk, INT STS-1Clk Processor SClk Interface RLOL CS RxON RESET RxClkINV Clock HOST/HW Invert RxClk Synthesizer Peak Detector STS-1/DS3 E3 HDB3/ RPOS REQEN Clock & Data Jitter AGC/ Slicer MUX B3ZS RNEG/ RTIP Recovery Attenuator Decoder Equalizer LCV RRING LOS SR/DR Remote Detector Local LoopBack RLB LLB LoopBack RLOS JATx/Rx TTIP TPOS HDB3/ Line Tx Jitter Timing MUX B3ZS Driver TNEG Pulse Attenuator TRING Encoder Control Shaping TxClk TAOS MTIP Device MRING Tx Monitor TxLEV Control TxON DMO Note: Serial Processor Interface input pins are shared by inHos Mode and redefined in theHardwar Mode. TRANSMIT INTERFACE CHARACTERISTICS Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the line Integrated Pulse Shaping Circuit. Built-in B3ZS/HDB3 Encoder (which can be disabled). Accepts Transmit Clock with duty cycle of 30%-70%. Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications. Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and ANSI T1.102 1993. Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE. Transmitter can be turned off in order to support redundancy designs. RECEIVE INTERFACE CHARACTERISTICS Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery. Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications. Meets Jitter Tolerance Requirements, as specified in ITU-T G.823 1993 for E3 Applications. Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications. Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms. Built-in B3ZS/HDB3 Decoder (which can be disabled). 2