XRT8000ID-F MaxLinear

XRT8000 Clock Synchronizer/Adapter for Communications September 2006 FEATURES D Clock Adaptation for Most Popular D Cascadable Telecommunication Frequencies D No External Components Needed D Wide Input Frequency Range D Lock Detect Indication Pin D Programmable Output Frequencies APPLICATIONS D Less than 0.05UI Wide Band Output Jitter D DSUs, CSUs and Access Equipment D Low Power Operation (5V and 3.3V) D ISDN Terminals D Maximum Lock Time of 45mS D Concentrators and Multiplexers GENERAL DESCRIPTION The XRT8000 is a dual phase-locked loop chip that to generate 1.544MHz or 2.048MHz output clocks. The generates two simultaneous, very low jitter, output clocks SLAVE (FORWARD, REVERSE) modes generate the for synchronization applications in wide area networking same output frequencies as the MASTER (FORWARD/ REVERSE MODES) except that the input frequency (F ) systems. The outputs are phase locked to the input IN signal. The chip has four basic modes of operation is 8kHz. An optional divide by eight can be enabled at each of the outputs. referred to as master (FORWARD, REVERSE) and slave (FORWARD, REVERSE) modes (See Figure 1). In the FORWARD mode it accepts up to 16th harmonic of either The input and output frequency selection can be done 1.544MHz or 2.048MHz as input reference and generates through a serial microprocessor interface. The XRT8000 1.2kHz and multiples of 2.4kHz, 56kHz or 64kHz. In the is available in either 18 pin SOIC package or 18 pin plastic REVERSE mode an input clock of 56kHz or 64kHz is used DIP. ORDERING INFORMATION Operating Temperature Part No. Package Range XRT8000IP 18 Lead 300 Mil PDIP -40C to +85C XRT8000ID 18 Lead 300 Mil JEDEC SOIC -40C to +85C XRT8000 XRT8000 XRT8000 K x 56kHz B CLK2 CLK2 CLK2 1 <= K <= 32 K x 64kHz T1 (1.544) n x 1.544 T1 56kHz 8kHz 1.2kHz or F A F F A/ B IN IN IN 2.4 x K E1 (2.048) 64kHz n x 2.048 E1 to CLK1 CLK1 1 <= n <= 16 CLK1 43.2kHz 1 <= K <= 18 SYNC SYNC SYNC 8kHz SLAVE MASTER FORWARD MASTER REVERSE FORWARD/REVERSE Figure 1. System Diagram Rev.1.11 E1999--2006 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 z www.exar.comXRT8000 BLOCK DIAGRAM Div. Analog Post By PhaseLocked Driver CLK2 Divider 8 Loop Q Feedback Q2 Divider DIV/8 EN M PLL 2 Lock M2 LOCKDET Detector SYNC Div. Input Analog F Post IN By Divider PhaseLocked Driver CLK1 Divider P 8 Loop Q V CC Feedback Divider M R R PLL 1 100K 100K M2 Q2 DIV/8 EN SCLK Serial CSB Mode and Frequency Select Control Interface SDI SDO MSB Figure 2. Block Diagram Rev. 1.11 2