XRT86VL30 T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL DECEMBER 2009 REV. 1.0.4 Receive LAPD Message frames from the incoming GENERAL DESCRIPTION T1/E1/J1 data stream and write the contents into the The XRT86VL30 is a single channel T1/E1/J1 BITS Receive HDLC buffers. The framer also contains a clock recovery element and framer and LIU Transmit and Overhead Data Input port, which 3 permits Data Link Terminal Equipment direct access integrated solution featuring R technology to the outbound T1/E1/J1 frames. Likewise, a (Relayless, Reconfigurable, Redundancy). The Receive Overhead output data port permits Data Link physical interface is optimized with internal Terminal Equipment direct access to the Data Link impedance, and with the patented pad structure, the bits of the inbound T1/E1/J1 frames. XRT86VL30 provides protection from power failures and hot swapping. The XRT86VL30 fully meets all of the latest T1/E1/J1 specifications: ANSI T1.101-1999, ANSI T1/E1.107- The XRT86VL30 contains an integrated DS1/E1/J1 1988, ANSI T1/E1.403-1995, ANSI T1/E1.231-1993, framer and LIU which provides DS1/E1/J1 framing ANSI T1/E1.408-1990, AT&T TR 62411 (12-90) and error accumulation in accordance with ANSI/ TR54016, and ITU G-703 (Including Section 13 - ITU T specifications. The framer has its own framing Synchronization), G.704, G706 and G.733, AT&T synchronizer and transmit-receive slip buffers. The Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT slip buffers can be independently enabled or disabled G.704, JT G706, I.431. Extensive test and diagnostic as required and can be configured to frame to the functions include Loop-backs, Boundary scan, common DS1/E1/J1 signal formats. Pseudo Random bit sequence (PRBS) test pattern The Framer block contains its own Transmit and generation, Performance Monitor, Bit Error Rate Receive T1/E1/J1 Framing function. There are 3 (BER) meter, forced error insertion, and LAPD Transmit HDLC controllers which encapsulate unchannelized data payload processing according to contents of the Transmit HDLC buffers into LAPD ITU-T standard Q.921. Message frames. There are 3 Receive HDLC APPLICATIONS AND FEATURES (NEXT PAGE) controllers which extract the payload content of FIGURE 1. XRT86VL30 SINGLE CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO External Data Link Controller Local PCM Highway Tx Overhead In Rx Overhead Out XRT86VL30 1:2 Turns Ratio TTIP 2-Frame Tx Serial Tx LIU Slip Buffer Tx Framer Data In Interface TRING Elastic Store Tx Serial Clock LLB LB 1:1 Turns Ratio RTIP 2-Frame Rx Serial Rx LIU Slip Buffer Rx Framer Data Out Interface RRING Elastic Store Rx Serial Clock PRBS LIU & Performance HDLC/LAPD Generator & Loopback RxLOS Monitor Controllers Analyser Control Line Side 8kHz sync OSC DMA Microprocessor Signaling & Interface JTAG Interface Alarms Back Plane 1.544-16.384 Mbit/s WR 4 3 ALE AS INT P System (Terminal) Side RD D 7:0 A 11:0 Select RDY DTACK TxON Intel/Motorola P Memory Configuration, Control & Status Monitor Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com ST-BUSXRT86VL30 T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL REV. 1.0.4 APPLICATIONS BITS Timing High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems SONET/SDH terminal or Add/Drop multiplexers (ADMs) T1/E1/J1 add/drop multiplexers (MUX) Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1 Digital Access Cross-connect System (DACs) Digital Cross-connect Systems (DCS) Frame Relay Switches and Access Devices (FRADS) ISDN Primary Rate Interfaces (PRA) PBXs and PCM channel bank T3 channelized access concentrators and M13 MUX Wireless base stations ATM equipment with integrated DS1 interfaces Multichannel DS1 Test Equipment T1/E1/J1 Performance Monitoring Voice over packet gateways Routers FEATURES Supports Section 13 - Synchronization Interface in ITU G.703 for both Transmit and Receive Paths Supports SSM Synchronous Messaging Generation (BOC for T1, National Bits for E1) on the Transmit Path Supports SSM Synchronous Messaging Extraction (BOC for T1, National Bits for E1) on the Receive Path Supports BITS timing generation on the Transmit Outputs Supports BITS timing extraction from NRZ data on the Analog Receive Path Parallel Microcontroller Interface Independent, full duplex DS1 Tx and Rx Framer/LIUs Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz asynchronous back plane connections with jitter and wander attenuation Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus Programmable output clocks for Fractional T1/E1/J1 Supports Channel Associated Signaling (CAS) Supports Common Channel Signalling (CCS) Supports ISDN Primary Rate Interface (ISDN PRI) signaling Extracts and inserts robbed bit signaling (RBS) 3 Integrated HDLC controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1) HDLC Controllers Support SS7 2