DS0102 Revision 17 IGLOO PLUS Low Power Flash FPGAs with Flash*Freeze Technology Advanced I/O Features and Benefits 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Bank-Selectable I/O Voltages4 Banks per Chip on All Low Power IGLOO PLUS Devices 1.2 V to 1.5 V Core Voltage Support for Low Power Single-Ended I/O Standards: LVTTL, LVCMOS Supports Single-Voltage System Operation 3.3V /2.5V / 1.8V /1.5V/1.2V 5 W Power Consumption in Flash*Freeze Mode Selectable Schmitt Trigger Inputs Low Power Active FPGA Operation Wide Range Power Supply Voltage Support per JESD8-B, Flash*Freeze Technology Enables Ultra-Low Power Allowing I/Os to Operate from 2.7 V to 3.6 V Consumption while Maintaining FPGA Content Wide Range Power Supply Voltage Support per JESD8-12, Configurable Hold Previous State, Tristate, HIGH, or LOW State Allowing I/Os to Operate from 1.14 V to 1.575 V per I/O in Flash*Freeze Mode I/O Registers on Input, Output, and Enable Paths Easy Entry To / Exit From Ultra-Low Power Flash*Freeze Mode Hot-Swappable and Cold-Sparing I/Os Feature Rich Programmable Output Slew Rate and Drive Strength 30 k to 125 k System Gates Weak Pull-Up/-Down Up to 36 kbits of True Dual-Port SRAM IEEE 1149.1 (JTAG) Boundary Scan Test Up to 212 User I/Os Pin-Compatible Small-Footprint Packages across the IGLOO PLUS Family Reprogrammable Flash Technology 130-nm, 7-Layer Metal, Flash-Based CMOS Process Clock Conditioning Circuit (CCC) and PLL Instant On Level 0 Support Six CCC Blocks, One with an Integrated PLL Single-Chip Solution Configurable Phase Shift, Multiply/Divide, Delay Capabilities, Retains Programmed Design When Powered Off and External Feedback 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Wide Input Frequency Range (1.5 MHz up to 250 MHz) Performance Embedded Memory In-System Programming (ISP) and Security 1 kbit of FlashROM User Nonvolatile Memory ISP Using On-Chip 128-Bit Advanced Encryption Standard SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM (AES) Decryption via JTAG (IEEE 1532compliant) Blocks (1, 2, 4, 9, and 18 organizations) FlashLock Designed to Secure FPGA Contents True Dual-Port SRAM (except 18) High-Performance Routing Hierarchy Segmented, Hierarchical Routing and Clock Structure Table 1 IGLOO PLUS Product Family IGLOO PLUS Devices AGLP030 AGLP060 AGLP125 System Gates 30,000 60,000 125,000 Typical Equivalent Macrocells 256 512 1,024 VersaTiles (D-flip-flops) 792 1,584 3,120 Flash*Freeze Mode (typical, W) 5 10 16 RAM Kbits (1,024 bits) 18 36 4,608-Bit Blocks 4 8 Secure (AES) ISP Yes Yes FlashROM Kbits 1 1 1 1 Integrated PLL in CCCs 1 1 2 VersaNet Globals 618 18 I/O Banks 4 4 4 Maximum User I/Os 120 157 212 Package Pins CS CS201, CS289 CS201, CS289 CS281, CS289 VQ VQ128 VQ176 Notes: 1. AGLP060 in CS201 does not support the PLL. 2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125. The AGLP030 device does not support this feature. December 2015 I 2015 Microsemi CorporationIGLOO PLUS Low Power Flash FPGAs 1 I/Os Per Package IGLOO PLUS Devices AGLP030 AGLP060 AGLP125 Package Single-Ended I/Os CS201 120 157 CS281 212 CS289 120 157 212 VQ128 101 VQ176 137 Note: When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single- ended user I/Os available is reduced by one. Table 2 IGLOO PLUS FPGAs Package Size Dimensions Package CS201 CS281 CS289 VQ128 VQ176 Length Width (mm/mm) 8 8 10 10 14 14 14 14 20 20 Nominal Area (mm2) 64 100 196 196 400 Pitch (mm) 0.5 0.5 0.8 0.4 0.4 Height (mm) 0.89 1.05 1.20 1.0 1.0 IGLOO PLUS Device Status IGLOO PLUS Device Status AGLP030 Production AGLP060 Production AGLP125 Production II Revision 17