AT17F040 and AT17F080 FPGA Configuration Flash Memory DATASHEET Features Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) 3.3V Output Capability 5.0V Tolerant I/O Pins Program Support using the Atmel ATDH2200E System, ATDH2225 ISP cable, or Third-party Programmers In-System Programmable (ISP) via 2-wire Bus Simple Interface to SRAM FPGAs Compatible with Atmel AT40K and AT94K Devices, Altera FLEX , APEX Devices, Lucent ORCA FPGAs, Xilinx XC3000, XC4000, XC5200, Spartan , Virtex FPGAs, and Motorola MPA1000 FPGAs Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Low-power CMOS FLASH Process Available in 6mm x 6mm x 1mm 8-pad LAP (Pin-compatible with 8-lead SOIC/VOIC Packages) and 20-lead PLCC Packages Emulation of the Atmel AT24C Serial EEPROMs Low-power Standby Mode Single Device Capable of Holding 4-Bitstream Files Allowing Simple System Reconfiguration Fast Serial Download Speeds up to 33MHz Endurance: 100,000 Write Cycles Typical Green (Pb/Halide-free/RoHS Compliant) Package Options Description The Atmel AT17F Series of In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory solution for FPGAs. The AT17F Series devices are packaged in the 8-pad LAP and 20-lead PLCC packages (Table 1-1). The AT17F Series Configurators use a simple serial-access procedure to configure one or more FPGA devices. The AT17F Series Configurators can be programmed with industry-standard programmers, the Atmel ATDH2200E Programming Kit or the Atmel ATDH2225 ISP Cable. Table 1. AT17F Series Packages Package AT17F040 AT17F080 8-pad LAP Yes Yes 20-lead PLCC Yes Yes Atmel-3039M-CNFG-AT17F040-080-Datasheet 0120151. Pin Configurations Table 1-1. Pin Descriptions (1) DATA Three-state DATA Output for Configuration. Open-collector bi-directional pin for programming. (1) CLK Clock Input. Used to increment the internal address and bit counter for reading and programming. Enable Page Download Mode Input. When PAGE EN is high the configuration download address space is partitioned into four equal pages. This gives users the ability to easily store and retrieve (2) PAGE EN multiple configuration bitstreams from a single configuration device. This input works in conjunction with the PAGESEL inputs. PAGE EN must be remain low if paging is not desired. When SER EN is Low (ISP mode) this pin has no effect. Page Select Input. Used to determine which of the four memory pages are targeted during a serial (2) PAGESEL 1:0 configuration download. The address space for each of the pages is shown in Table 1-2. When SER EN is Low (ISP mode) these pins have no effect. Output Enable (Active High) and RESET (Active Low) when SER EN is High. A Low level on (1) RESET/OE RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. Chip Enable Input (Active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit (1) CE counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode (SER EN Low). GND Ground. A 0.2F decoupling capacitor between V and GND is recommended. CC Chip Enable Output (when SER EN is High). This output goes Low when the internal address counter has reached its maximum value. If the PAGE EN input is set High, the maximum value is the highest address in the selected partition. The PAGESEL 1:0 inputs are used to make the four partition selections. If the PAGE EN input is set Low, the device is not partitioned and the address CEO maximum value is the highest address in the device (Table 1-2). In a daisy chain of AT17F Series devices, the CEO pin of one device must be connected to the CE input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low thereafter, CEO will stay High until the entire EEPROM is read again. Device Selection Input, (when SER EN Low). The input is used to enable (or chip select) the (1) A2 device during programming (i.e., when SER EN is Low). Refer to the Atmel AT17F Programming Specification available on the Atmel web site for additional details. Open Collector Reset State Indicator. Driven Low during power-up reset, released when power-up READY is complete. (recommended 4.7k pull-up on this pin if used). Serial Enable Input. Must remain High during FPGA configuration operations. Bringing SER EN (1) SER EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER EN should be tied to V . CC V Device Power Supply. +3.3V (10%) CC Notes: 1. Internal 20K pull-up resistor 2. Internal 30K pull-up resistor 2 AT17F040/080 DATASHEET Atmel-3039M-CNFG-AT17F040-080-Datasheet 012015