Features Fast read access time 55ns Low-power CMOS operation 100A max standby 40mA max active at 5MHz JEDEC standard packages 40-lead PDIP 44-lead PLCC Direct upgrade from 512Kbit, 1Mbit, and 2Mbit 4Mb (256K x 16) Atmel AT27C516, AT27C1024, and AT27C2048) EPROMs One-time 5V 10% supply High-reliability CMOS technology Programmable, 2,000V ESD protection Read-only Memory 200mA latchup immunity Rapid programming algorithm 50s/word (typical) CMOS- and TTL-compatible inputs and outputs Atmel AT27C4096 Integrated product identification code Industrial temperature range Green (Pb/halide-free) packaging option 1. Description The Atmel AT27C4096 is a low-power, high-performance, 4,194,304-bit, one-time pro- grammable, read-only memory (OTP EPROM) organized as 256K by 16 bits. It requires a single 5V power supply in normal read mode operation. Any word can be accessed in less than 55ns, eliminating the need for speed reducing WAIT states. The x16 organization makes this part ideal for high-performance, 16- and 32-bit microprocessor systems. In read mode, the AT27C4096 typically consumes 15mA. Standby mode supply current is typically less than 10A The AT27C4096 is available in industry-standard, JEDEC-approved, one-time programma- ble (OTP) PDIP and PLCC packages. The device features two-line control (CE, OE) to eliminate bus contention in high speed systems. With high-density 256K word storage capability, the AT27C4096 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. The AT27C4096 has additional features that ensure high quality and efficient production use. The rapid programming algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 50s/word. The Inte- grated product identification code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper pro- gramming algorithms and voltages. 0311JEPROM4/112. Pin configurations 40-lead PDIP 44-lead PLCC Pin name Function Top view Top view A0 - A17 Addresses O0 - O15 Outputs VPP 1 40 VCC CE 2 39 A17 CE Chip enable O15 3 38 A16 O12 7 39 A13 OE Output enable O14 4 37 A15 O11 8 38 A12 O13 5 36 A14 O10 9 37 A11 NC No connect O12 6 35 A13 O9 10 36 A10 O11 7 34 A12 O8 11 35 A9 Note: Both GND pins must be O10 8 33 A11 GND 12 34 GND connected O9 9 32 A10 NC 13 33 NC O8 10 31 A9 O7 14 32 A8 GND 11 30 GND O6 15 31 A7 O7 12 29 A8 O5 16 30 A6 O6 13 28 A7 O4 17 29 A5 O5 14 27 A6 O4 15 26 A5 O3 16 25 A4 O2 17 24 A3 O1 18 23 A2 O0 19 22 A1 OE 20 21 A0 3. System considerations Switching between active and standby conditions via the chip enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device nonconformance. At a minimum, a 0.1F, high-frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V and ground terminals of the device, as close to the device as possible. CC Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7F bulk electrolytic capacitor should be utilized, again connected between the V and ground terminals. This capacitor should be positioned as CC close as possible to the point where the power supply is connected to the array. Figure 3-1. Block diagram 2 Atmel AT27C4096 0311JEPROM4/11 O3 18 6 O13 O2 19 5 O14 O1 20 4 O15 O0 21 3 CE OE 22 2 VPP NC 23 1 NC A0 24 44 VCC A1 25 43 A17 A2 26 42 A16 A3 27 41 A15 A4 28 40 A14