Features Fast read access time 45ns Low-power CMOS operation 100A max standby 20mA max active at 5MHz JEDEC standard packages 28-lead PDIP 32-lead PLCC 5V 10% supply 512K (64K x 8) High-reliability CMOS technology One-time 2,000V ESD protection 200mA latchup immunity Programmable, Rapid programming algorithm 100s/byte (typical) Read-only Memory CMOS- and TTL-compatible inputs and outputs Integrated product identification code Industrial and automotive temperature ranges Atmel AT27C512R Green (Pb/halide-free) packaging option 1. Description The Atmel AT27C512R is a low-power, high-performance, 524,288-bit, one-time pro- grammable, read-only memory (OTP EPROM) organized as 64K by 8 bits. It requires only one 5V power supply in normal read mode operation. Any byte can be accessed in less than 45ns, eliminating the need for speed reducing WAIT states on high-performance micropro- cessor systems. The Atmel scaled CMOS technology provides high speed, lower active power consumption, and significantly faster programming. Power consumption is typically only 8mA in active mode and less than 10A in standby mode. The AT27C512R is available in a choice of industry-standard, JEDEC-approved, one-time programmable (OTP) PDIP and PLCC packages. All devices feature two-line control (CE, OE) to give designers the flexibility to prevent bus contention. With 64K byte storage capability, the AT27C512R allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. The AT27C512R has additional features to ensure high quality and efficient production use. The rapid programming algorithm reduces the time required to program the part and guar- antees reliable programming. Programming time is typically only 100s/byte. The integrated product identification code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper pro- gramming algorithms and voltages. 0015PEPROM10/112. Pin configurations 28-lead PDIP 32-lead PLCC Pin name Function Top view Top view A0 - A15 Addresses O0 - O7 Outputs A15 1 28 VCC A12 2 27 A14 CE Chip enable A7 3 26 A13 A6 5 29 A8 A6 4 25 A8 OE/VPP Output enable/ Program supply A5 6 28 A9 A5 5 24 A9 A4 7 27 A11 NC No connect A4 6 23 A11 A3 8 26 NC A3 7 22 OE/VPP A2 9 25 OE/VPP A2 8 21 A10 A1 10 24 A10 A1 9 20 CE A0 11 23 CE A0 10 19 O7 NC 12 22 O7 O0 11 18 O6 O0 13 21 O6 O1 12 17 O5 O2 13 16 O4 GND 14 15 O3 Note: PLCC package pins 1 and 17 are dont connect 3. System considerations Switching between active and standby conditions via the chip enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device nonconformance. At a minimum, a 0.1F, high-frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V and ground terminals of the device, as close to the device as possible. CC Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7F bulk electrolytic capacitor should be utilized, again connected between the V and ground terminals. This capacitor should be positioned as CC close as possible to the point where the power supply is connected to the array. Figure 3-1. Block diagram 2 Atmel AT27C512R 0015PEPROM10/11 O1 14 4 A7 O2 15 3 A12 GND 16 2 A15 NC 17 1 NC O3 18 32 VCC O4 19 31 A14 O5 20 30 A13