Features High Performance, Low Power 32-bit Atmel AVR Microcontroller Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set Read-Modify-Write Instructions and Atomic Bit Manipulation Performing up to 1.51DMIPS/MHz Up to 126 DMIPS Running at 84MHz from Flash (1 Wait-State) Up to 63 DMIPS Running at 42MHz from Flash (0 Wait-State) Memory Protection Unit Multi-Layer Bus System 32-bit AVR High-Performance Data Transfers on Separate Buses for Increased Performance 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral Microcontroller Communication 4 generic DMA Channels for High Bandwidth Data Paths Internal High-Speed Flash 256KBytes, 128KBytes, 64KBytes versions AT32UC3A3256S Single-Cycle Flash Access up to 36MHz AT32UC3A3256 Prefetch Buffer Optimizing Instruction Execution at Maximum Speed 4 ms Page Programming Time and 8ms Full-Chip Erase Time AT32UC3A3128S 100,000 Write Cycles, 15-year Data Retention Capability AT32UC3A3128 Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM AT32UC3A364S 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus AT32UC3A364 64KBytes (2x32KBytes with independent access) on the Multi-Layer Bus System Interrupt Controller AT32UC3A4256S Autovectored Low Latency Interrupt Service with Programmable Priority AT32UC3A4256 System Functions Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator AT32UC3A4128S Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL), AT32UC3A4128 Watchdog Timer, Real-Time Clock Timer External Memories AT32UC3A464S Support SDRAM, SRAM, NandFlash (1-bit and 4-bit ECC), Compact Flash Up to 66 MHz AT32UC3A464 External Storage device support MultiMediaCard (MMC V4.3), Secure-Digital (SD V2.0), SDIO V1.1 CE-ATA V1.1, FastSD, SmartMedia, Compact Flash Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro IDE Interface One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S, AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications Buffer Encryption/Decryption Capabilities Universal Serial Bus (USB) High-Speed USB 2.0 (480Mbit/s) Device and Embedded Host Flexible End-Point Configuration and Management with Dedicated DMA Channels On-Chip Transceivers Including Pull-Ups One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs. Two Three-Channel 16-bit Timer/Counter (TC) Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) Fractionnal Baudrate Generator 32072H-AVR3210/2012AT32UC3A3 Support for SPI and LIN Optionnal support for IrDA, ISO7816, Hardware Handshaking, RS485 interfaces and Modem Line Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals One Synchronous Serial Protocol Controller Supports I2S and Generic Frame-Based Protocols Two Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible 16-bit Stereo Audio Bitstream Sample Rate Up to 50 KHz QTouch Library Support Capacitive Touch Buttons, Sliders, and Wheels QTouch and QMatrix Acquisition On-Chip Debug System (JTAG interface) Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace 110 General Purpose Input/Output (GPIOs) Standard or High Speed mode Toggle capability: up to 84MHz Packages 144-ball TFBGA, 11x11 mm, pitch 0.8 mm 144-pin LQFP, 22x22 mm, pitch 0.5 mm 100-ball VFBGA, 7x7 mm, pitch 0.65 mm Single 3.3V Power Supply 2 32072HAVR3210/2012